Cirrus Logic EP73xx User Manual
Page 55
EP7309/11/12 User’s Manual - DS508UM4
4-9
Copyright Cirrus Logic, Inc. 2003
Interrupt Controller
44
4
MCINT:
Media changed interrupt. This interrupt will be active after a
rising edge on the
nMEDCHG
input pin has been detected, This
input is de-glitched with a 16 kHz clock so it will only generate an
interrupt if it is active for longer than 125
µs. It is mapped to the
FIQ input on the ARM7TDMI processor and is cleared by writing
to the MCEOI location. On power-up, the Media change pin
(
nMEDCHG
) is used as an input to force the processor to either
boot from the internal Boot ROM, or from external memory. After
power-up, the pin can be used as a general purpose FIQ interrupt
pin.
CSINT:
CODEC sound interrupt, generated when the data FIFO has
reached half full or empty (depending on the interface direction).
It is cleared by writing to the COEOI location.
EINT1:
External interrupt input 1. This interrupt will be active if the
nEINT1
input is active (low). It is cleared by returning
nEINT1
to
the passive (high) state.
EINT2:
External interrupt input 2. This interrupt will be active if the
nEINT2
input is active (low). It is cleared by returning
nEINT2
to
the passive (high) state.
EINT3:
External interrupt input 3. This interrupt will be active if the
EINT3
input is active (high). It is cleared by returning
EINT3
to the
passive (low) state.
TC1OI:
TC1 under flow interrupt. This interrupt becomes active on the
next falling edge of the timer counter 1 clock after the timer
counter has under flowed (reached zero). It is cleared by writing
to the TC1EOI location.
TC2OI:
TC2 under flow interrupt. This interrupt becomes active on the
next falling edge of the timer counter 2 clock after the timer
counter has under flowed (reached zero). It is cleared by writing
to the TC2EOI location.
RTCMI:
RTC compare match interrupt. This interrupt becomes active on
the next rising edge of the 1 Hz Real Time Clock (one second later)
after the 32-bit time written to the Real Time Clock match register
exactly matches the current time in the RTC. It is cleared by
writing to the RTCEOI location.
TINT:
64 Hz tick interrupt. This interrupt becomes active on every rising
edge of the internal 64 Hz clock signal. This 64 Hz clock is derived
from the 15-stage ripple counter that divides the 32.768 kHz
oscillator input down to 1 Hz for the Real Time Clock. This
interrupt is cleared by writing to the TEOI location. TINT is
disabled/turned off during the Standby State.