Table 5-3: adc sample clock settings -6 – Cirrus Logic EP73xx User Manual
Page 66
5-6
EP7309/11/12 User’s Manual - DS508UM4
Copyright Cirrus Logic, Inc. 2003
System Registers
5
ADCKSEL: Microwire/SPI peripheral clock speed select. This two bit field
selects the frequency of the ADC sample clock, which is twice the
frequency of the synchronous serial ADC interface clock. The
table below shows the available frequencies for operation when
the CPU is operated in either PLL mode or in 13 MHz external
clock mode. These bits are also used to select the master mode
shift clock frequency for the SSI2 interface when set into master
mode.
EXCKEN: External expansion clock enable. If this bit is set, the
EXPCLK
is
enabled continuously as a free running clock assuming that the
main oscillator is running. Refer to CLKCTL bits[1-2] on
SYSCON3.
EXPCLK
corresponds to the memory bus frequency in
the table provided. This bit should not be left set all the time for
power consumption reasons. If the system enters the Standby
State, the
EXPCLK
will become undefined. If this bit is clear,
EXPCLK
will be active during memory cycles to expansion slots
that have external wait state generation enabled only.
WAKEDIS: Setting this bit disables waking up from the Standby State, via the
wakeup input.
IRTXM:
IrDA TX mode bit. This bit controls the IrDA encoding strategy.
Clearing this bit means that each zero bit transmitted is
represented as a pulse of width 3/16th of the bit rate period.
Setting this bit means each zero bit is represented as a pulse of
width 3/16th of the period of 115,200-bit rate clock (i.e., 1.6 ms
regardless of the selected bit rate).
*
Setting this bit will use less
power, but will probably reduce transmission distances.
* The pulse width will be reduced by 22.5% when operating at 90.3168 MHz.
Table 5-3: ADC Sample Clock Settings
ADCKSEL
ADC Sample Frequency (kHz) — SMPCLK
ADC Clock Frequency (kHz) — ADCCLK
90 MHz
PLL Clock
13 MHz EXTCLK
90 MHz
PLL Clock
13 MHz EXTCLK
00
9.8
8
8.4
4.9
4
4.2
01
39.2
32
33.8
19.6
16
16.9
10
156.8
128
135.4
78.4
64
67.7
11
313.6
256
270.8
156.8
128
135.4