Cirrus Logic EP73xx - Manual (Page 19)

EP7309/11/12 User’s Manual - DS508UM4 1-5
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Copyright Cirrus Logic, Inc. 2003
Introduction
11
1
0x8000.0540 PALLSW 0 RW 32 Least significant 32-bit word of LCD palette register page 9-8
0x8000.0580 PALMSW 0 RW 32 Most significant 32-bit word of LCD palette register page 9-8
0x8000.05C0 STFCLR — WR — Write to clear all start up reason flags page 5-13
0x8000.0600 BLEOI — WR — Write to clear battery low interrupt page 4-13
0x8000.0640 MCEOI — WR — Write to clear media changed interrupt page 4-13
0x8000.0680 TEOI — WR — Write to clear tick and watchdog interrupt page 4-13
0x8000.06C0 TC1EOI — WR — Write to clear TC1 interrupt page 4-13
0x8000.0700 TC2EOI — WR — Write to clear TC2 interrupt page 4-14
0x8000.0740 RTCEOI — WR — Write to clear RTC match interrupt page 4-14
0x8000.0780 UMSEOI — WR — Write to clear UART modem status changed interrupt page 4-14
0x8000.07C0 COEOI — WR — Write to clear CODEC sound interrupt page 4-14
0x8000.0800 HALT — WR — Write to enter the Idle State page 2-14
0x8000.0840 STDBY — WR — Write to enter the Standby State page 2-13
0x8000.0880–
0x8000.0FFF
Reserved Write will have no effect, read is undefined
0x8000.1000 FBADDR 0xC RW 4 LCD frame buffer start address page 9-9
0x8000.1100 SYSCON2 0 RW 16 System control register 2 page 5-7
0x8000.1140 SYSFLG2 0 RD 24 System status register 2 page 5-12
0x8000.1240 INTSR2 0 RD 16 Interrupt status register 2 page 4-11
0x8000.1280 INTMR2 0 RW 16 Interrupt mask register 2 page 4-12
0x8000.12C0–
0x8000.147F
Reserved Write will have no effect, read is undefined
0x8000.1480 UARTDR2 0 RW 16 UART2 Data Register page 17-5
0x8000.14C0 UBRLCR2 0 RW 32 UART2 bit rate and line control register page 17-6
0x8000.1500 SS2DR 0 RW 16 Master / slave SSI2 data Register page 16-20
0x8000.1600 SRXEOF — WR — Write to clear RX FIFO overflow flag page 4-14
0x8000.16C0 SS2POP — WR — Write to pop SSI2 residual byte into RX FIFO page 16-20
0x8000.1700 KBDEOI — WR — Write to clear keyboard interrupt page 4-14
0x8000.1800 Reserved — WR —
Do not write to this location. A write will cause the
processor to go into an unsupported power savings
state.
0x8000.1840–
0x8000.1FFF
Reserved — Write will have no effect, read is undefined
0x8000.2000 DAIR 0 RW 32 DAI control register page 16-12
0x8000.2040 DAIR0 0 RW 32 DAI data register 0 page 16-14
0x8000.2080 DAIDR1 0 RW 32 DAI data register 1 page 16-15
0x8000.20C0 DAIDR2 0 WR 21 DAI data register 2 page 16-16
0x8000.2100 DAISR 0 RW 32 DAI status register page 16-16
0x8000.2200 SYSCON3 0 RW 16 System control register 3 page 5-8
0x8000.2240 INTSR3 0 RD 32 Interrupt status register 3 page 4-12
0x8000.2280 INTMR3 0 RW 8 Interrupt mask register 3 page 4-13
Table 1-2: EP73xx Internal Registers (Little Endian Mode) (Continued)
Address Name Default RD/WR Size Comments Page