Document Outline

• Title Page
• Copyright and Disclaimer
• List of Figures
• List of Tables
• About This Manual
  • Who Should Read This Manual
  • Related Publications
  • Conventions Used in This Manual
  • Using This Manual with the Programming Environments Manual
• 1. PowerPC 750GX Overview
  • 1.1 750GX Microprocessor Overview
  • 1.2 750GX Microprocessor Features
    • 1.2.1 Instruction Flow
      • 1.2.1.1 Instruction Queue and Dispatch Unit
      • 1.2.1.2 Branch Processing Unit (BPU)
      • 1.2.1.3 Completion Unit
    • 1.2.2 Independent Execution Units
      • 1.2.2.1 Integer Units (IUs)
      • 1.2.2.2 Floating-Point Unit (FPU)
      • 1.2.2.3 Load/Store Unit (LSU)
      • 1.2.2.4 System Register Unit (SRU)
    • 1.2.3 Memory Management Units (MMUs)
    • 1.2.4 On-Chip Level 1 Instruction and Data Caches
    • 1.2.5 On-Chip Level 2 Cache Implementation
    • 1.2.6 System Interface/Bus Interface Unit (BIU)
    • 1.2.7 Signals
    • 1.2.8 Signal Configuration
    • 1.2.9 Clocking
  • 1.3 750GX Microprocessor Implementation
  • 1.4 PowerPC Registers and Programming Model
  • 1.5 Instruction Set
    • 1.5.1 PowerPC Instruction Set
    • 1.5.2 750GX Microprocessor Instruction Set
  • 1.6 On-Chip Cache Implementation
    • 1.6.1 PowerPC Cache Model
    • 1.6.2 750GX Microprocessor Cache Implementation
  • 1.7 Exception Model
    • 1.7.1 PowerPC Exception Model
    • 1.7.2 750GX Microprocessor Exception Implementation
  • 1.8 Memory Management
    • 1.8.1 PowerPC Memory-Management Model
    • 1.8.2 750GX Microprocessor Memory-Management Implementation
  • 1.9 Instruction Timing
  • 1.10 Power Management
  • 1.11 Thermal Management
  • 1.12 Performance Monitor
• 2. Programming Model
  • 2.1 PowerPC 750GX Processor Register Set
    • 2.1.1 Register Set
    • 2.1.2 PowerPC 750GX-Specific Registers
      • 2.1.2.1 Instruction Address Breakpoint Register (IABR)
      • 2.1.2.2 Hardware-Implementation-Dependent Register 0 (HID0)
      • 2.1.2.3 Hardware-Implementation-Dependent Register 1 (HID1)
      • 2.1.2.4 Hardware-Implementation-Dependent Register 2 (HID2)
      • 2.1.2.5 Performance-Monitor Registers
    • 2.1.3 Instruction Cache Throttling Control Register (ICTC)
    • 2.1.4 Thermal-Management Registers (THRMn)
      • 2.1.4.1 Thermal-Management Registers 1-2 (THRM1-THRM2)
      • 2.1.4.2 Thermal-Management Register 3 (THRM3)
      • 2.1.4.3 Thermal-Management Register 4 (THRM4)
    • 2.1.5 L2 Cache Control Register (L2CR)
  • 2.2 Operand Conventions
    • 2.2.1 Data Organization in Memory and Data Transfers
    • 2.2.2 Alignment and Misaligned Accesses
    • 2.2.3 Floating-Point Operand and Execution Models-UISA
      • 2.2.3.1 Denormalized Number Support
      • 2.2.3.2 Non-IEEE Mode (Nondenormalized Mode)
      • 2.2.3.3 Time-Critical Floating-Point Operation
      • 2.2.3.4 Floating-Point Storage Access Alignment
      • 2.2.3.5 Optional Floating-Point Graphics Instructions
  • 2.3 Instruction Set Summary
    • 2.3.1 Classes of Instructions
      • 2.3.1.1 Definition of Boundedly Undefined
      • 2.3.1.2 Defined Instruction Class
      • 2.3.1.3 Illegal Instruction Class
      • 2.3.1.4 Reserved Instruction Class
    • 2.3.2 Addressing Modes
      • 2.3.2.1 Memory Addressing
      • 2.3.2.2 Memory Operands
      • 2.3.2.3 Effective Address Calculation
      • 2.3.2.4 Synchronization
    • 2.3.3 Instruction Set Overview
    • 2.3.4 PowerPC UISA Instructions
      • 2.3.4.1 Integer Instructions
      • 2.3.4.2 Floating-Point Instructions
      • 2.3.4.3 Load-and-Store Instructions
      • 2.3.4.4 Branch and Flow-Control Instructions
      • 2.3.4.5 System Linkage Instruction-UISA
      • 2.3.4.6 Processor Control Instructions-UISA
      • 2.3.4.7 Memory Synchronization Instructions-UISA
    • 2.3.5 PowerPC VEA Instructions
      • 2.3.5.1 Processor Control Instructions-VEA
      • 2.3.5.2 Memory Synchronization Instructions-VEA
      • 2.3.5.3 Memory Control Instructions-VEA
      • 2.3.5.4 Optional External Control Instructions
    • 2.3.6 PowerPC OEA Instructions
      • 2.3.6.1 System Linkage Instructions-OEA
      • 2.3.6.2 Processor Control Instructions-OEA
      • 2.3.6.3 Memory Control Instructions-OEA
    • 2.3.7 Recommended Simplified Mnemonics
• 3. Instruction-Cache and Data-Cache Operation
  • 3.1 Data-Cache Organization
  • 3.2 Instruction-Cache Organization
  • 3.3 Memory and Cache Coherency
    • 3.3.1 Memory/Cache Access Attributes (WIMG Bits)
    • 3.3.2 MEI Protocol
      • 3.3.2.1 MEI Hardware Considerations
    • 3.3.3 Coherency Precautions in Single-Processor Systems
    • 3.3.4 Coherency Precautions in Multiprocessor Systems
    • 3.3.5 PowerPC 750GX-Initiated Load/Store Operations
      • 3.3.5.1 Performed Loads and Stores
      • 3.3.5.2 Sequential Consistency of Memory Accesses
      • 3.3.5.3 Atomic Memory References
  • 3.4 Cache Control
    • 3.4.1 Cache-Control Parameters in HID0
      • 3.4.1.1 Data-Cache Flash Invalidation
      • 3.4.1.2 Enabling and Disabling the Data Cache
      • 3.4.1.3 Locking the Data Cache
      • 3.4.1.4 Instruction-Cache Flash Invalidation
      • 3.4.1.5 Enabling and Disabling the Instruction Cache
      • 3.4.1.6 Locking the Instruction Cache
    • 3.4.2 Cache-Control Instructions
      • 3.4.2.1 Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst)
      • 3.4.2.2 Data Cache Block Zero (dcbz)
      • 3.4.2.3 Data Cache Block Store (dcbst)
      • 3.4.2.4 Data Cache Block Flush (dcbf)
      • 3.4.2.5 Data Cache Block Invalidate (dcbi)
      • 3.4.2.6 Instruction Cache Block Invalidate (icbi)
  • 3.5 Cache Operations
    • 3.5.1 Cache-Block-Replacement/Castout Operations
    • 3.5.2 Cache Flush Operations
    • 3.5.3 Data-Cache Block-Fill Operations
    • 3.5.4 Instruction-Cache Block-Fill Operations
    • 3.5.5 Data-Cache Block-Push Operations
  • 3.6 L1 Caches and 60x Bus Transactions
    • 3.6.1 Read Operations and the MEI Protocol
    • 3.6.2 Bus Operations Caused by Cache-Control Instructions
    • 3.6.3 Snooping
    • 3.6.4 Snoop Response to 60x Bus Transactions
    • 3.6.5 Transfer Attributes
  • 3.7 MEI State Transactions
• 4. Exceptions
  • 4.1 PowerPC 750GX Microprocessor Exceptions
  • 4.2 Exception Recognition and Priorities
  • 4.3 Exception Processing
    • 4.3.1 Machine Status Save/Restore Register 0 (SRR0)
    • 4.3.2 Machine Status Save/Restore Register 1 (SRR1)
    • 4.3.3 Machine State Register (MSR)
    • 4.3.4 Enabling and Disabling Exceptions
    • 4.3.5 Steps for Exception Processing
    • 4.3.6 Setting MSR[RI]
    • 4.3.7 Returning from an Exception Handler
  • 4.4 Process Switching
  • 4.5 Exception Definitions
    • 4.5.1 System Reset Exception (0x00100)
      • 4.5.1.1 Soft Reset
      • 4.5.1.2 Hard Reset
    • 4.5.2 Machine-Check Exception (0x00200)
      • 4.5.2.1 Machine-Check Exception Enabled (MSR[ME] = 1)
      • 4.5.2.2 Checkstop State (MSR[ME] = 0)
    • 4.5.3 DSI Exception (0x00300)
    • 4.5.4 ISI Exception (0x00400)
    • 4.5.5 External Interrupt Exception (0x00500)
    • 4.5.6 Alignment Exception (0x00600)
    • 4.5.7 Program Exception (0x00700)
    • 4.5.8 Floating-Point Unavailable Exception (0x00800)
    • 4.5.9 Decrementer Exception (0x00900)
    • 4.5.10 System Call Exception (0x00C00)
    • 4.5.11 Trace Exception (0x00D00)
    • 4.5.12 Floating-Point Assist Exception (0x00E00)
    • 4.5.13 Performance-Monitor Interrupt (0x00F00)
    • 4.5.14 Instruction Address Breakpoint Exception (0x01300)
    • 4.5.15 System Management Interrupt (0x01400)
    • 4.5.16 Thermal-Management Interrupt Exception (0x01700)
    • 4.5.17 Data Address Breakpoint Exception
      • 4.5.17.1 Data Address Breakpoint Register (DABR)
    • 4.5.18 Soft Stops
    • 4.5.19 Exception Latencies
    • 4.5.20 Summary of Front-End Exception Handling
    • 4.5.21 Timer Facilities
    • 4.5.22 External Access Instructions
• 5. Memory Management
  • 5.1 MMU Overview
    • 5.1.1 Memory Addressing
    • 5.1.2 MMU Organization
    • 5.1.3 Address-Translation Mechanisms
    • 5.1.4 Memory-Protection Facilities
    • 5.1.5 Page History Information
    • 5.1.6 General Flow of MMU Address Translation
      • 5.1.6.1 Real-Addressing Mode and Block-Address-Translation Selection
      • 5.1.6.2 Page-Address-Translation Selection
    • 5.1.7 MMU Exceptions Summary
    • 5.1.8 MMU Instructions and Register Summary
  • 5.2 Real-Addressing Mode
  • 5.3 Block-Address Translation
  • 5.4 Memory Segment Model
    • 5.4.1 Page History Recording
      • 5.4.1.1 Referenced Bit
      • 5.4.1.2 Changed Bit
      • 5.4.1.3 Scenarios for Referenced and Changed Bit Recording
    • 5.4.2 Page Memory Protection
    • 5.4.3 TLB Description
      • 5.4.3.1 TLB Organization
      • 5.4.3.2 TLB Invalidation
    • 5.4.4 Page-Address-Translation Summary
    • 5.4.5 Page Table-Search Operation
    • 5.4.6 Page Table Updates
    • 5.4.7 Segment Register Updates
• 6. Instruction Timing
  • 6.1 Terminology and Conventions
  • 6.2 Instruction Timing Overview
  • 6.3 Timing Considerations
    • 6.3.1 General Instruction Flow
    • 6.3.2 Instruction Fetch Timing
      • 6.3.2.1 Cache Arbitration
      • 6.3.2.2 Cache Hit
      • 6.3.2.3 Cache Miss
      • 6.3.2.4 L2 Cache Access Timing Considerations
      • 6.3.2.5 Instruction Dispatch and Completion Considerations
      • 6.3.2.6 Rename Register Operation
      • 6.3.2.7 Instruction Serialization
  • 6.4 Execution-Unit Timings
    • 6.4.1 Branch Processing Unit Execution Timing
      • 6.4.1.1 Branch Folding
      • 6.4.1.2 Branch Instructions and Completion
      • 6.4.1.3 Branch Prediction and Resolution
    • 6.4.2 Integer Unit Execution Timing
    • 6.4.3 Floating-Point Unit Execution Timing
    • 6.4.4 Effect of Floating-Point Exceptions on Performance
    • 6.4.5 Load/Store Unit Execution Timing
    • 6.4.6 Effect of Operand Placement on Performance
    • 6.4.7 Integer Store Gathering
    • 6.4.8 System Register Unit Execution Timing
  • 6.5 Memory Performance Considerations
    • 6.5.1 Caching and Memory Coherency
    • 6.5.2 Effect of TLB Miss
  • 6.6 Instruction Scheduling Guidelines
    • 6.6.1 Branch, Dispatch, and Completion-Unit Resource Requirements
      • 6.6.1.1 Branch-Resolution Resource Requirements
      • 6.6.1.2 Dispatch-Unit Resource Requirements
      • 6.6.1.3 Completion-Unit Resource Requirements
  • 6.7 Instruction Latency Summary
• 7. Signal Descriptions
  • 7.1 Signal Configuration
  • 7.2 Signal Descriptions
    • 7.2.1 Address-Bus Arbitration Signals
      • 7.2.1.1 Bus Request (BR)-Output
      • 7.2.1.2 Bus Grant (BG)-Input
      • 7.2.1.3 Address Bus Busy (ABB)
    • 7.2.2 Address Transfer Start Signals
      • 7.2.2.1 Transfer Start (TS)
    • 7.2.3 Address Transfer Signals
      • 7.2.3.1 Address Bus (A[0-31])
      • 7.2.3.2 Address-Bus Parity (AP[0-3])
    • 7.2.4 Address Transfer Attribute Signals
      • 7.2.4.1 Transfer Type (TT[0-4])
      • 7.2.4.2 Transfer Size (TSIZ[0-2])-Output
      • 7.2.4.3 Transfer Burst (TBST)
      • 7.2.4.4 Cache Inhibit (CI)-Output
      • 7.2.4.5 Write-Through (WT)-Output
      • 7.2.4.6 Global (GBL)
    • 7.2.5 Address Transfer Termination Signals
      • 7.2.5.1 Address Acknowledge (AACK)-Input
      • 7.2.5.2 Address Retry (ARTRY)
    • 7.2.6 Data-Bus Arbitration Signals
      • 7.2.6.1 Data-Bus Grant (DBG)-Input
      • 7.2.6.2 Data-Bus Write-Only (DBWO)
      • 7.2.6.3 Data Bus Busy (DBB)
    • 7.2.7 Data-Transfer Signals
      • 7.2.7.1 Data Bus (DH[0-31], DL[0-31])
      • 7.2.7.2 Data-Bus Parity (DP[0-7])
      • 7.2.7.3 Data Bus Disable (DBDIS)-Input
    • 7.2.8 Data-Transfer Termination Signals
      • 7.2.8.1 Transfer Acknowledge (TA)-Input
      • 7.2.8.2 Data Retry (DRTRY)-Input
      • 7.2.8.3 Transfer Error Acknowledge (TEA)-Input
    • 7.2.9 System Status Signals
      • 7.2.9.1 Interrupt (INT)- Input
      • 7.2.9.2 System Management Interrupt (SMI)-Input
      • 7.2.9.3 Machine-Check Interrupt (MCP)-Input
      • 7.2.9.4 Checkstop Input (CKSTP_IN)-Input
      • 7.2.9.5 Checkstop Output (CKSTP_OUT)-Output
    • 7.2.10 Reset Signals
      • 7.2.10.1 Hard Reset (HRESET)-Input
      • 7.2.10.2 Soft Reset (SRESET)-Input
    • 7.2.11 Processor Status Signals
      • 7.2.11.1 Quiescent Request (QREQ)-Output
      • 7.2.11.2 Quiescent Acknowledge (QACK)-Input
      • 7.2.11.3 Reservation (RSRV)-Output
      • 7.2.11.4 Time Base Enable (TBEN)-Input
      • 7.2.11.5 TLB Invalidate Synchronize (TLBISYNC)-Input
    • 7.2.12 Processor Mode Selection Signals
    • 7.2.13 I/O Voltage Select Signals
    • 7.2.14 Test Interface Signals
      • 7.2.14.1 IEEE 1149.1a-1993 Interface Description
      • 7.2.14.2 LSSD_MODE
      • 7.2.14.3 L1_TSTCLK
      • 7.2.14.4 L2_TSTCLK
      • 7.2.14.5 BVSEL
    • 7.2.15 Clock Signals
      • 7.2.15.1 System Clock (SYSCLK)-Input
      • 7.2.15.2 Clock Out (CLK_OUT)-Output
      • 7.2.15.3 PLL Configuration (PLL_CFG[0:4])-Input
      • 7.2.15.4 PLL Range (PLL_RNG[0:1])-Input
    • 7.2.16 Power and Ground Signals
• 8. Bus Interface Operation
  • 8.1 Bus Interface Overview
    • 8.1.1 Operation of the Instruction and Data L1 Caches
    • 8.1.2 Operation of the Bus Interface
    • 8.1.3 Bus Signal Clocking
    • 8.1.4 Optional 32-Bit Data Bus Mode
    • 8.1.5 Direct-Store Accesses
  • 8.2 Memory-Access Protocol
    • 8.2.1 Arbitration Signals
    • 8.2.2 Miss-under-Miss
      • 8.2.2.1 Miss-under-Miss and System Performance
      • 8.2.2.2 Speculative Loads and Conditional Branches
  • 8.3 Address-Bus Tenure
    • 8.3.1 Address-Bus Arbitration
    • 8.3.2 Address Transfer
      • 8.3.2.1 Address-Bus Parity
      • 8.3.2.2 Address Transfer Attribute Signals
      • 8.3.2.3 Burst Ordering During Data Transfers
      • 8.3.2.4 Effect of Alignment in Data Transfers
      • 8.3.2.5 Alignment of External Control Instructions
    • 8.3.3 Address Transfer Termination
  • 8.4 Data-Bus Tenure
    • 8.4.1 Data-Bus Arbitration
      • 8.4.1.1 Using the DBB Signal
    • 8.4.2 Data-Bus Write-Only
    • 8.4.3 Data Transfer
    • 8.4.4 Data-Transfer Termination
      • 8.4.4.1 Normal Single-Beat Termination
      • 8.4.4.2 Data-Transfer Termination Due to a Bus Error
    • 8.4.5 Memory Coherency-MEI Protocol
  • 8.5 Timing Examples
  • 8.6 Optional Bus Configuration
    • 8.6.1 32-Bit Data Bus Mode
    • 8.6.2 No-DRTRY Mode
  • 8.7 Processor State Signals
    • 8.7.1 Support for the lwarx and stwcx. Instruction Pair
    • 8.7.2 TLBISYNC Input
  • 8.8 IEEE 1149.1a-1993 Compliant Interface
    • 8.8.1 JTAG/COP Interface
  • 8.9 Using Data-Bus Write-Only
• 9. L2 Cache
  • 9.1 L2 Cache Overview
  • 9.2 L2 Cache Operation
  • 9.3 L2 Cache Control Register (L2CR)
  • 9.4 L2 Cache Initialization
  • 9.5 L2 Cache Global Invalidation
  • 9.6 L2 Cache Used as On-Chip Memory
    • 9.6.1 Locking the L2 Cache
      • 9.6.1.1 Loading the Locked L2 Cache
      • 9.6.1.2 Locked Cache Operation
  • 9.7 Data-Only and Instruction-Only Modes
  • 9.8 L2 Cache Test Features and Methods
    • 9.8.1 L2CR Support for L2 Cache Testing
    • 9.8.2 L2 Cache Testing
  • 9.9 L2 Cache Timing
• 10. Power and Thermal Management
  • 10.1 Dynamic Power Management
  • 10.2 Programmable Power Modes
    • 10.2.1 Power Management Modes
      • 10.2.1.1 Full On Mode
      • 10.2.1.2 Doze Mode
      • 10.2.1.3 Nap Mode
      • 10.2.1.4 Sleep Mode
      • 10.2.1.5 Dynamic Power Reduction
    • 10.2.2 Power Management Software Considerations
  • 10.3 750GX Dual PLL Feature
    • 10.3.1 Overview
    • 10.3.2 Configuration Restriction on Frequency Transitions
    • 10.3.3 Dual PLL Implementation
  • 10.4 Thermal Assist Unit
    • 10.4.1 Thermal Assist Unit Overview
    • 10.4.2 Thermal Assist Unit Operation
      • 10.4.2.1 TAU Single-Threshold Mode
      • 10.4.2.2 TAU Dual-Threshold Mode
      • 10.4.2.3 750GX Junction Temperature Determination
      • 10.4.2.4 Power Saving Modes and TAU Operation
  • 10.5 Instruction-Cache Throttling
• 11. Performance Monitor and System Related Features
  • 11.1 Performance-Monitor Interrupt
  • 11.2 Special-Purpose Registers Used by Performance Monitor
    • 11.2.1 Performance-Monitor Registers
      • 11.2.1.1 Monitor Mode Control Register 0 (MMCR0)
      • 11.2.1.2 User Monitor Mode Control Register 0 (UMMCR0)
      • 11.2.1.3 Monitor Mode Control Register 1 (MMCR1)
      • 11.2.1.4 User Monitor Mode Control Register 1 (UMMCR1)
      • 11.2.1.5 Performance-Monitor Counter Registers (PMCn)
      • 11.2.1.6 User Performance-Monitor Counter Registers (UPMC1-UPMC4)
      • 11.2.1.7 Sampled Instruction Address Register (SIA)
      • 11.2.1.8 User Sampled Instruction Address Register (USIA)
  • 11.3 Event Counting
  • 11.4 Event Selection
  • 11.5 Notes
  • 11.6 Debug Support
    • 11.6.1 Overview
    • 11.6.2 Data-Address Breakpoint
  • 11.7 JTAG/COP Functions
    • 11.7.1 Introduction
    • 11.7.2 Processor Resources Available through JTAG/COP Serial Interface
  • 11.8 Resets
    • 11.8.1 Hard Reset
    • 11.8.2 Soft Reset
    • 11.8.3 Reset Sequence
  • 11.9 Checkstops
    • 11.9.1 Checkstop Sources
    • 11.9.2 Checkstop Control Bits
    • 11.9.3 Open-Collector-Driver States during Checkstop
    • 11.9.4 Vacancy Slot Application
  • 11.10 750GX Parity
    • 11.10.1 Parity Control and Status
    • 11.10.2 Enabling Parity Error Detection
    • 11.10.3 Parity Errors
• Acronyms and Abbreviations
• Index
• Revision Log