IBM POWERPC 750GL - Manual (Page 71)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006 Programming Model
Page 71 of 377
2.1.2.4 Hardware-Implementation-Dependent Register 2 (HID2)
The Hardware-Implementation-Dependent Register 2 (HID2) enables parity. The status bits (25:27) are set
when a parity error is detected and cleared by writing '0' to each bit. See the IBM PowerPC 750GX RISC
Microprocessor Datasheet for details.
HID2 can be accessed with mtspr and mfspr using SPR 1016.
Reserved
ST
M
U
MD
Reserved
FI
CBP
FI
TB
P
FDCB
P
FDT
B
P
F
L2T
B
P
IC
PS
DCP
S
L2PS Res
e
rv
ed
IC
PE
DCP
E
L2PE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Bits Field Name Description Notes
0:2 Reserved Reserved 1
3 STMUMD
Disable store miss-under-miss processing (changes the allowed outstanding store
misses from two to one.
4:19 Reserved Reserved 1
20 FICBP Force instruction-cache bad parity.
21 FITBP Force instruction-tag bad parity.
22 FDCBP Force data-cache bad parity.
23 FDTBP Force data-tag bad parity.
24 FL2TBP Force L2-tag bad parity.
25 ICPS L1 instruction-cache/instruction-tag parity error status/mask.
26 DCPS L1 data-cache/data-tag parity error status/mask.
27 L2PS L2 tag parity error status/mask.
28 Reserved Reserved. 1
29 ICPE Enable L1 instruction-cache/instruction-tag parity checking.
30 DCPE Enable L1 data-cache/data-tag parity checking.
31 L2PE Enable L2 tag parity checking.
1. Reserved. Used as factory test bits. Do not change from their power-up state unless indicated to do so.