IBM POWERPC 750GL - Manual (Page 251)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_07.fm.(1.2)
March 27, 2006 Signal Descriptions
Page 251 of 377
7.2 Signal Descriptions
This section summarizes the functions of individual signals on the 750GX, grouped according to Figure 7-1.
Chapter 8, Bus Interface Operation, on page 279 describes many of these signals in greater detail, both with
respect to how individual signals function and to how the groups of signals interact. The information in the
remainder of this chapter applies to the basic transfer protocol of the 60x bus. This is the normal transfer
protocol used by 60x devices. The extended transfer protocol (also referred to as ETP or PLL 0 internal
configuration [PI0] protocol) is not supported by the 750GX.
Note: In the following tables, “cycle” or “clock” refers to a single bus clock period, which corresponds to one
or more internal processor clocks depending on the clock mode programmed for the 750GX.
Note: In phase-locked loop (PLL)-bypass mode, the SYSCLK input signal clocks the internal processor
directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for fac-
tory use only.
7.2.1 Address-Bus Arbitration Signals
The address arbitration signals are the input and output signals the 750GX uses to request the address bus,
recognize when the request is granted, and indicate to other devices when mastership is granted.
For a detailed description of how these signals interact, see Section 8.3.1, Address-Bus Arbitration, on
page 290.
7.2.1.1 Bus Request (BR)—Output
State Asserted Indicates that the 750GX has a bus transaction to perform, and that it is
waiting for a qualified bus grant (BG) to begin the address tenure. BR might
be asserted even if all four (five with snoop) possible address tenures have
already been granted.
Negated Indicates that the 750GX does not have a bus transaction to perform, or, if
parked, that it is potentially ready to start a bus transaction on the next clock
(with proper qualification, see BG).
Timing Assertion Occurs on any cycle. Will not occur if the 750GX is parked and the address
bus is idle (BG asserted and address bus busy [ABB] input negated).
Negation Occurs during the cycle TS is asserted even if another transaction is
pending. Also occurs the cycle after any qualified ARTRY on the bus unless
this chip asserted the ARTRY and requires it to perform a snoop copyback.
Will also occur if the bus request is internally cancelled before receiving a
qualified BG.
High
Impedance Occurs during a hard reset or checkstop condition.