IBM POWERPC 750GL - Manual (Page 125)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_03.fm.(1.2)
March 27, 2006 Instruction-Cache and Data-Cache Operation
Page 125 of 377
3.3 Memory and Cache Coherency
The primary objective of a coherent memory system is to provide the same image of memory to all devices
using the system. Coherency allows synchronization and cooperative use of shared resources. Otherwise,
multiple copies of a memory location, some containing stale values, could exist in a system resulting in errors
when the stale values are used. Each potential bus master must follow rules for managing the state of its
cache. This section describes the coherency mechanisms of the PowerPC Architecture and the 3-state
cache-coherency protocol of the 750GX’s data cache.
Note that unless specifically noted, the discussion of coherency in this section applies to the 750GX’s data
cache only. The instruction cache is not snooped. Instruction-cache coherency must be maintained by soft-
ware. However, the 750GX does support a fast instruction-cache invalidate capability as described in
Section 3.4.1.4 on page 133.
3.3.1 Memory/Cache Access Attributes (WIMG Bits)
Some memory characteristics can be set on either a block or page basis by using the WIMG bits in the block-
address-translation (BAT) registers or page table entry (PTE), respectively. The WIMG attributes control the
following functionality:
• Write-through (W bit)
• Caching-inhibited (I bit)
• Memory coherency (M bit)
• Guarded memory (G bit)
Figure 3-3. Instruction-Cache Organization
8 Words/Block
128 Sets
Way 5
Way 6
Way 7
Way 4 Address Tag 4
Address Tag 5
Address Tag 6
Address Tag 7
Way 1
Way 2
Way 3
Way 0 Address Tag 0
Address Tag 1
Address Tag 2
Address Tag 3
Valid
Valid
Valid
Words [0–7]
Valid
Words [0–7]
Words [0–7]
Words [0–7]
Valid
Valid
Valid
Words [0–7]
Valid
Words [0–7]
Words [0–7]
Words [0–7]