IBM POWERPC 750GL - Manual (Page 270)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Signal Descriptions
Page 270 of 377
gx_07.fm.(1.2)
March 27, 2006
7.2.9 System Status Signals
Most system status signals are input signals that indicate when exceptions are received, when checkstop
conditions have occurred, and when the 750GX must be reset. The 750GX generates the output signal,
CKSTP_OUT, when it detects a checkstop condition.
7.2.9.1 Interrupt (INT)— Input
7.2.9.2 System Management Interrupt (SMI)—Input
Timing Assertion/
Negation Assertion might occur on any cycle during the normal or extended data-bus
tenure for the 750GX (during DBB, and the cycle after TA during reads).
Assertion should occur for one cycle only.
It is the responsibility of the system to ensure that TEA is negated by the
start of the next data-bus tenure.
State Asserted The 750GX initiates an interrupt if MSR[EE] is set. Otherwise, the 750GX
ignores the interrupt. To guarantee that the 750GX will take the external
interrupt, INT must be held active until the 750GX takes the interrupt. Other-
wise, whether the 750GX takes an external interrupt depends on whether
the MSR[EE] bit was set while the INT signal was held active.
Negated Indicates that normal operation should proceed.
Timing Assertion May occur at any time and may be asserted asynchronously to the input
clocks. The INT input is level-sensitive.
Negation Should not occur until an interrupt is taken.
State Asserted The 750GX initiates a system management interrupt operation if the
MSR[EE] is set. Otherwise, the 750GX ignores the exception condition. The
system must hold SMI active until the exception is taken.
Negated Indicates that normal operation should proceed.
Timing Assertion May occur at any time and may be asserted asynchronously to the input
clocks. The SMI input is level-sensitive.
Negation Should not occur until an interrupt is taken.