IBM POWERPC 750GL - Manual (Page 53)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_01.fm.(1.2)
March 27,2006 PowerPC 750GX Overview
Page 53 of 377
Note: Figure 1-5 does not show features such as reservation stations and rename buffers that reduce stalls
and improve instruction throughput.
The instruction pipeline in the 750GX has four major pipeline stages. They are fetch, dispatch, execute, and
complete:
• The fetch pipeline stage primarily involves fetching instructions from the memory system and keeping the
instruction queue full. The BPU decodes branches after they are fetched and removes (folds out) those
that do not update the CTR or LR from the instruction stream. If the branch is taken or predicted as taken,
the fetch unit is informed of the new address and fetching resumes along the taken path. For branches
not taken or predicted as not taken, sequential fetching continues.
• The dispatch unit is responsible for taking instructions from the bottom two locations of the instruction
queue and delivering them to an execution unit for further processing. Dispatch is responsible for decod-
ing the instructions and determining which instructions can be dispatched. To qualify for dispatch, a reser-
vation station, a rename buffer, and a position in the completion queue all must be available. A branch
instruction could be processed by the BPU on the same clock cycle for a maximum of three instructions
dispatched per cycle.
The dispatch stage accesses operands, assigns a rename buffer for operands that update architected
registers, which include the GPRs, FPRs, and CR, and delivers the instruction to the reservation registers
of the respective execution units. If a source operand is not available because a previous instruction is
updating the item in a rename buffer, dispatch provides a tag that indicates which rename buffer will sup-
ply the operand when it becomes available. At the end of the dispatch stage, the instructions are removed
from the instruction queue, latched into reservation stations at the appropriate execution unit, and
assigned positions in the completion buffers in sequential program order.
Figure 1-5. Pipeline Diagram
Fetch
Complete (Write-Back)
Dispatch
Execute Stage
FPU3
SRU IU2 IU1
Maximum 3-instruction dispatch per
clock cycle (includes one branch instruc-
tion)
Maximum 2-instruction completion
per clock cycle
FPU2
FPU1
LSU1
Maximum 4-instruction fetch per
clock cycle
LSU2
BPU