2 cache flush operations, Table 3-2, Plru bit update rules – IBM POWERPC 750GL User Manual
Page 138: Table 3-3, Plru replacement block selection
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction-Cache and Data-Cache Operation
Page 138 of 377
gx_03.fm.(1.2)
March 27, 2006
If all eight blocks are valid, then a block is selected for replacement according to the PLRU bit encodings
shown in Table 3-3.
During power-up or hard reset, all the valid bits of the blocks are cleared, and the PLRU bits cleared to point
to block L0 of each set. Note that this is also the state of the data or instruction cache after setting their
respective flash invalidate bit, HID0[DCFI] or HID0[ICFI].
3.5.2 Cache Flush Operations
The instruction cache can be invalidated by executing a series of icbi instructions or by setting HID0[ICFI].
The data cache can be invalidated by executing a series of dcbi instructions or by setting HID0[DCFI].
Any modified entries in the data cache can be copied back to memory (flushed) by using the dcbf instruction
or by executing a series of 12 uniquely addressed load or dcbz instructions to each of the 128 sets. The
address space should not be shared with any other process to prevent snoop hit invalidations during the
flushing routine. Exceptions should be disabled during this time so that the PLRU algorithm is not disturbed.
Table 3-2. PLRU Bit Update Rules
If the current
access is to:
Then the PLRU bits are changed to:
B0
B1
B2
B3
B4
B5
B6
L0
1
1
x
1
x
x
x
L1
1
1
x
0
x
x
x
L2
1
0
x
x
1
x
x
L3
1
0
x
x
0
x
x
L4
0
x
1
x
x
1
x
L5
0
x
1
x
x
0
x
L6
0
x
0
x
x
x
1
L7
0
x
0
x
x
x
0
1. x = Does not change
Table 3-3. PLRU Replacement Block Selection
If the PLRU bits are:
Then the block
selected for
replacement is:
B0
0
B1
0
B3
0
L0
0
0
1
L1
0
1
B4
0
L2
0
1
1
L3
1
B2
0
B5
0
L4
1
0
1
L5
1
1
B6
0
L6
1
1
1
L7