IBM POWERPC 750GL - Manual (Page 260)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Signal Descriptions
Page 260 of 377
gx_07.fm.(1.2)
March 27, 2006
7.2.4.4 Cache Inhibit (CI)—Output
The cache inhibit (CI) signal is an output signal on the 750GX.
7.2.4.5 Write-Through (WT)—Output
The write-through (WT) signal is an output signal on the 750GX.
State Asserted Indicates that a single-beat transfer will not be cached, reflecting the setting
of the I bit for the block or page that contains the address of the current
transaction.
Negated Indicates that a burst transfer will allocate the 750GX data-cache block.
Timing Assertion/
Negation/
High
Impedance The same as A[0–31].
State Asserted Indicates that a single-beat write transaction is write-through, reflecting the
value of the W bit for the block or page that contains the address of the
current transaction. Assertion during a read operation indicates a data load.
Negated Indicates that a write transaction is not write-through. During a read opera-
tion, negation indicates an instruction load.
Timing Assertion/
Negation/
High
Impedance The same as A[0–31].