4 process switching, 5 exception definitions, 4 process switching 4.5 exception definitions – IBM POWERPC 750GL User Manual
Page 162: Table 4-5, Msr setting due to exception
User’s Manual
IBM PowerPC 750GX and GL RISC Microprocessor
Exceptions
Page 162 of 377
gx_04.fm.(1.2)
March 27, 2006
4.4 Process Switching
The following instructions are useful for restoring proper context during process switching:
• The Synchronization (sync) instruction orders the effects of instruction execution. All instructions previ-
ously initiated appear to have completed before the sync instruction completes, and no subsequent
instructions appear to be initiated until the sync instruction completes. For an example using sync, see
Chapter 2, “PowerPC Register Set” of the PowerPC Microprocessor Family: The Programming Environ-
ments Manual.
• The Instruction Synchronization (isync) instruction waits for all previous instructions to complete and
then discards any fetched instructions, causing subsequent instructions to be fetched (or refetched) from
memory and to execute in the context (privilege, translation, and protection) established by the previous
instructions.
• The stwcx. instruction clears any outstanding reservations, ensuring that an lwarx instruction in an old
process is not paired with an stwcx. instruction in a new one.
The operating system should set MSR[RI] as described in Section 4.3.6, Setting MSR[RI],.
4.5 Exception Definitions
Table 4-5 shows all the types of exceptions that can occur with the 750GX and MSR settings when the
processor goes into supervisor mode due to an exception. Depending on the exception, certain of these bits
are stored in SRR1 when an exception is taken.
Table 4-5. MSR Setting Due to Exception
(Page 1 of 2)
Exception Type
MSR Bit
POW
ILE
EE
PR
FP
ME
FE0
SE
BE
FE1
IP
IR
DR
PM
RI
LE
System reset
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
Machine check
0
—
0
0
0
0
0
0
0
0
—
0
0
0
0
ILE
DSI
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
ISI
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
External interrupt
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
Alignment
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
Program
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
Floating-point unavailable
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
Decrementer interrupt
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
System call
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
Trace exception
0
—
0
0
0
—
0
0
0
0
—
0
0
0
0
ILE
Note:
1. A zero indicates that the bit is cleared.
2. The ILE bit is copied from the MSR[ILE].
3. A dash indicates that the bit is not altered.
4. Reserved bits are read as if written as 0.