IBM POWERPC 750GL - Manual (Page 246)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Instruction Timing
Page 246 of 377
gx_06.fm.(1.2)
March 27, 2006
Store Floating-Point
Double
stfd 54 — LSU 2:1 —
Store Floating-Point
Double with Update
stfdu 55 — LSU 2:1 —
Store Floating-Point
Double with Update
Indexed
stfdux 31 759 LSU 2:1 —
Store Floating-Point
Double Indexed
stfdx 31 727 LSU 2:1 —
Store Floating-Point as
Integer Word Indexed
stfiwx 31 983 LSU 2:1 —
Store Floating-Point
Single
stfs 52 — LSU 2:1 —
Store Floating-Point
Single with Update
stfsu 53 — LSU 2:1 —
Store Floating-Point
Single with Update
Indexed
stfsux 31 695 LSU 2:1 —
Store Floating-Point
Single Indexed
stfsx 31 663 LSU 2:1 —
Store Halfword sth 44 — LSU 2:1 —
Store Halfword Byte-
Reverse Indexed
sthbrx 31 918 LSU 2:1 —
Store Halfword with
Update
sthu 45 — LSU 2:1 —
Store Halfword with
Update Indexed
sthux 31 439 LSU 2:1 —
Store Halfword Indexed sthx 31 407 LSU 2:1 —
Store Multiple Word stmw 47 — LSU 2 + n 3 Execution
Store String Word
Immediate
stswi 31 725 LSU 2 + n 3 Execution
Store String Word
Indexed
stswx 31 661 LSU 2 + n 3 Execution
Store Word stw 36 — LSU 2:1 —
Store Word Byte-
Reverse Indexed
stwbrx 31 662 LSU 2:1 —
Store Word Conditional
Indexed
stwcx. 31 150 LSU 8:8 Execution
Store Word with Update stwu 37 — LSU 2:1 —
Table 6-9. Load-and-Store Instructions (Page 3 of 4)
Instruction Mnemonic
Primary
Opcode Extended
Opcode
Unit Cycles Serialization
1. For cache operations, the first number indicates the latency in finishing a single instruction; the second indicates the throughput for
back-to-back cache operations. Throughput might be larger than the initial latency, as more cycles might be needed to complete
the instruction to the cache, which stays busy keeping subsequent cache operations from executing.
2. The throughput number of six cycles for dcbz assumes it is to nonglobal (M = 0) address space. For global address space,
throughput is at least 11 cycles.
3. Load/store multiple/string instruction cycles are represented as a fixed number of cycles plus a variable number of cycles, where n
is the number of words accessed by the instruction.