IBM POWERPC 750GL - Manual (Page 73)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006 Programming Model
Page 73 of 377
User Monitor Mode Control Register 0 (UMMCR0)
The contents of MMCR0 are reflected to UMMCR0, which can be read by user-level software. MMCR0 can
be accessed with mfspr using SPR 936.
6 DISCOUNT
Disables counting of PMCn when a performance-monitor interrupt is signaled (that is,
((PMCnINTCONTROL = '1') & (PMCn[0] = '1') & (ENINT = '1')) or when an enabled time-
base transition occurs with ((INTONBITTRANS = '1') & (ENINT = '1')).
0 Signaling a performance-monitor interrupt does not affect the counting status of
PMCn.
1 Signaling a performance-monitor interrupt prevents changing of the PMC1
counter. The PMCn counter does not change if PMC2COUNTCTL = '0'.
Because a time-base signal could have occurred along with an enabled counter overflow
condition, software should always reset INTONBITTRANS to zero, if the value in INTON-
BITTRANS was a one.
7:8 RTCSELECT
64-bit time base, bit selection enable.
00
Pick bit 63 to count.
01 Pick bit 55 to count.
10 Pick bit 51 to count.
11 Pick bit 47 to count.
9 INTONBITTRANS
Cause interrupt signaling when the bit identified in RTCSELECT transitions from off to on.
0
Do not allow interrupt signal if chosen bit transitions.
1 Signal interrupt if chosen bit transitions.
Software is responsible for setting and clearing INTONBITTRANS.
10:15 THRESHOLD
Threshold value. The 750GX supports all six bits, allowing threshold values from 0–63.
The intent of the THRESHOLD support is to characterize L1 data-cache misses.
16 PMC1INTCONTROL
Enables interrupt signaling due to PMC1 counter overflow.
0 Disable PMC1 interrupt signaling due to PMC1 counter overflow.
1 Enable PMC1 interrupt signaling due to PMC1 counter overflow.
17 PMCINTCONTROL
Enable interrupt signaling due to any PMC2–PMC4 counter overflow. Overrides the set-
ting of DISCOUNT.
0 Disable PMC2–PMC4 interrupt signaling due to PMC2–PMC4 counter overflow.
1 Enable PMC2–PMC4 interrupt signaling due to PMC2–PMC4 counter overflow.
18 PMCTRIGGER
Can be used to trigger counting of PMC2–PMC4 after PMC1 has overflowed or after a
performance-monitor interrupt is signaled.
0
Enable PMC2–PMC4 counting.
1 Disable PMC2–PMC4 counting until either PMC1[0] = 1 or a performance-moni-
tor interrupt is signaled.
19:25 PMC1SELECT PMC1 input selector; 128 events selectable.
26:31 PMC2SELECT PMC2 input selector; 64 events selectable.
Bits Field Name Description