IBM POWERPC 750GL - Manual (Page 223)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_06.fm.(1.2)
March 27, 2006 Instruction Timing
Page 223 of 377
Figure 6-6. Instruction Timing—Cache Miss
6 fadd *
7 fadd *
1 fadd
0 add
10 11
8 add *
1 2 3 4 5 6 7 8 0
2 add
3 fadd
9 add *
4 b
10 add *
11 add *
12 fadd *
9
•••
3
2
1
0 7
9
8
5
4
3
2
3
2
1
0
3
2
1
3
2
1 3 6
7
6
9
8
7
6
1
0
Instruction
Queue
Completion
Queue
5 fsub
Address
Data
Fetch *
In dispatch entry (IQ0/IQ1)
Execute
Complete (In CQ)
In retirement entry (CQ0/CQ1)
7
6
13 fadd *
* Instructions 5 and 6 are not in the IQ in clock cycle 5. Here, the fetch stage shows cache latency.