IBM POWERPC 750GL User Manual
Page 374
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Index
Page 374 of 377
750gx_umIX.fm.(1.2)
March 27, 2006
DABR
DAR
,
DEC
,
DSISR
EAR
HID0
,
HID1
IABR
,
ICTC
,
L2CR
MMCR0
,
MMCR1
,
MSR
PMC1 and PMC2
PMCn
PVR
SDR1
SIA
,
SPRGn
,
SPRs for performance monitor
SRn
SRR0/SRR1
,
THRMn
,
time base (TB)
user-level
CR
CTR
FPRn
FPSCR
,
GPRn
LR
,
time base (TB)
UMMCR0
,
UMMCR1
,
UPMCn
USIA
,
XER
Rename buffer, definition
,
Rename register operation
Reservation station, definition
,
Reserved instruction class
,
Reset
HRESET signal
reset exception
SRESET signal
,
Retirement, definition
rfi
,
Rotate/shift instructions
,
RSRV (reserve) signal
S
SDR1 register
Segment registers
SR description
SR manipulation instructions
,
Segmented memory model, see Memory management
unit
Serializing instructions
,
Shift/rotate instructions
,
SIA (sampled instruction address) register
,
,
Signals
AACK
ABB
address arbitration
address transfer
address transfer attribute
An
ARTRY
,
,
BG
BR
,
,
CI
CKSTP_IN/CKSTP_OUT
,
,
configuration
COP/scan interface
,
data arbitration
,
data transfer termination
DBB
,
DBG
,
DBWO
,
,
,
DHn/DLn
DRTRY
,
GBL
HRESET
MCP
,
,
PLL_CFGn
power and ground signals
,
QACK
QREQ
,
RSRV
SRESET
TA
TBST
TEA
,
transfer encoding
,
TS
TSIZn
TTn
WT
Single-beat transfer
reads with data delays, timing
,
reads, timing
termination
,
writes, timing
Snooping
SPRGn registers
SRESET (soft reset) signal
,
SRR0/SRR1 (status save/restore registers)
description
,
exception processing
,
Stage, definition
,