IBM POWERPC 750GL - Manual (Page 298)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 298 of 377
gx_08.fm.(1.2)
March 27, 2006
Effect of Alignment in Data Transfers (32-Bit Bus)
The aligned data-transfer cases for 32-bit data-bus mode are shown in Table 8-6 on page 298. All of the
transfers require a single data beat (if caching-inhibited or write-through) except for double-word cases which
require two data beats. The double-word case is only generated by the 750GX for load or store double oper-
ations to or from the floating-point General Purpose Registers (GPRs). All caching-inhibited instruction
fetches are performed as word operations.
Table 8-5. Misaligned Data Transfers (4-Byte Examples)
Transfer Size
(Four Bytes)
TSIZ[0–2] A[29–31]
Data-Bus Byte Lanes
0 1 2 3 4 5 6 7
Aligned 1 0 0 0 0 0 A A A A — — — —
Misaligned—first access 0 1 1 0 0 1 A A A — — — —
second access 0 0 1 1 0 0 — — — — A — — —
Misaligned—first access 0 1 0 0 1 0 — — A A — — — —
second access 0 1 1 1 0 0 — — — — A A — —
Misaligned—first access 0 0 1 0 1 1 — — — A — — — —
second access 0 1 1 1 0 0 — — — — A A A —
Aligned 1 0 0 1 0 0 — — — — A A A A
Misaligned—first access 0 1 1 1 0 1 — — — — — A A A
second access 0 0 1 0 0 0 A — — — — — — —
Misaligned—first access 0 1 0 1 1 0 — — — — — — A A
second access 0 1 0 0 0 0 A A — — — — — —
Misaligned—first access 0 0 1 1 1 1 — — — — — — — A
second access 0 1 1 0 0 0 A A A — — — — —
Note:
A: Byte lane used
—: Byte lane not used
Table 8-6. Aligned Data Transfers (32-Bit Bus Mode) (Page 1 of 2)
Transfer Size TSIZ0 TSIZ1 TSIZ2 A[29–31]
Data-Bus Byte Lanes
0 1 2 3 4 5 6 7
Byte
0 0 1 000 A — — — x x x x
0 0 1 001 — A x — x x x x
0 0 1 010 — — A — x x x x
0 0 1 011 — — — A x x x x
0 0 1 100 A — — — x x x x
0 0 1 101 — A — — x x x x
0 0 1 110 — — A — x x x x
0 0 1 111 — — — A x x x x