Table 11-5, Pmc4 events—mmcr1[5:9] select encodings – IBM POWERPC 750GL User Manual

Page 354

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User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor

Performance Monitor and System Related Features

Page 354 of 377

gx_11.fm.(1.2)

March 27, 2006

Bits MMCR1[5:9] specify events associated with PMC4, as shown in Table 11-5.

The PMC registers can be accessed with the mtspr and mfspr instructions using the following SPR
numbers:

• PMC1 is SPR 953.
• PMC2 is SPR 954.
• PMC3 is SPR 957.
• PMC4 is SPR 958.

11.2.1.6 User Performance-Monitor Counter Registers (UPMC1–UPMC4)

The contents of the PMC1–PMC4 are reflected to UPMC1–UPMC4, which can be read by user-level soft-
ware. The UPMC registers can be read with the mfspr instructions using the following SPR numbers:

• UPMC1 is SPR 937.
• UPMC2 is SPR 938.
• UPMC3 is SPR 941.
• UPMC4 is SPR 942.

1 0000

Number of branches in the second speculative stream that resolve correctly.

1 0001

Number of cycles the BPU stalls due to LR or CR unresolved dependencies.

All others

Reserved. Might be used in a later revision.

Table 11-5. PMC4 Events—MMCR1[5:9] Select Encodings

Encoding

Comments

00000

Register holds current value

00001

Number of processor cycles

00010

Number of completed instructions, not including folded branches

00011

Number of transitions from 0 to 1 of specified bits in the Time Base Lower (TBL) register. Bits are specified through
RTCSELECT, MMCR0[7–8]. 00 = 31, 01 = 23, 10 = 19, 11 = 15

00100

Number of instructions dispatched. 0, 1, or 2 per cycle

00101

Number of L2 castouts

00110

Number of cycles spent performing table searches for DTLB accesses.

00111

Reserved. Might be used in a later revision.

01000

Number of mispredicted branches. Reserved for future use.

01001

Reserved. Might be used in a later revision.

01010

Number of store conditional instructions completed with reservation intact

01011

Number of completed sync instructions

01100

Number of snoop request retries

01101

Number of completed integer operations

01110

Number of cycles the branch processing unit (BPU) cannot process new branches due to having two unresolved
branches

All others

Reserved. Might be used in a later revision.

Table 11-4. PMC3 Events—MMCR1[0:4] Select Encodings

(Page 2 of 2)

Encoding

Description

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