IBM POWERPC 750GL - Manual (Page 219)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_06.fm.(1.2)
March 27, 2006 Instruction Timing
Page 219 of 377
Figure 6-5 on page 220 shows a simple example of instruction fetching that hits in the L1 cache. This
example uses a series of integer add and double-precision floating-point add instructions to show how the
number of instructions to be fetched is determined, how program order is maintained by the instruction and
completion queues, how instructions are dispatched and retired in pairs (maximum), and how the FPU, IU1,
and IU2 pipelines function. The following instruction sequence is examined.
0 add
1 fadd
2 add
3 fadd
4 b 6
5 fsub
6 fadd
7 fadd
8 add
9 add
10 add
11 add
12 fadd
13 add
14 fadd
15 •
16 •
17
•