IBM POWERPC 750GL - Manual (Page 99)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006 Programming Model
Page 99 of 377
Little Endian Misaligned Accesses
The 750GX supports misaligned single register load-and-store accesses in little-endian mode without causing
an alignment exception. However, execution of a load/store multiple or string instruction causes an alignment
exception.
Self-Modifying Code
When a processor modifies a memory location that might be contained in the instruction cache, software
must ensure that memory updates are visible to the instruction-fetching mechanism. This can be achieved by
the following instruction sequence:
dcbst # update memory
sync # wait for update
icbi # remove (invalidate) copy in instruction cache
isync # remove copy in own instruction buffer
These operations are required because the data cache is a write-back cache. Since instruction fetching
bypasses the data cache, changes to items in the data cache cannot be reflected in memory until the fetch
operations complete.
Special care must be taken to avoid coherency paradoxes in systems that implement unified secondary
caches, and designers should carefully follow the guidelines for maintaining cache coherency that are
provided in the VEA, and discussed in Chapter 5, “Cache Model and Memory Coherency,” in the PowerPC
Microprocessor Family: The Programming Environments Manual. Because the 750GX does not broadcast
the M bit for instruction fetches, external caches are subject to coherency paradoxes.
Integer Load-and-Store Address Generation
Integer load-and-store operations generate effective addresses using register indirect with immediate index
mode, register indirect with index mode, or register indirect mode. See Section 2.3.2.3 on page 90 for infor-
mation about calculating effective addresses. Note that in some implementations, operations that are not
naturally aligned might suffer performance degradation. See Section 4.5.6 on page 170 for additional infor-
mation about load-and-store address alignment exceptions.
Integer Load Instructions
For integer load instructions, the byte, half word, or word addressed by the EA is loaded into rD. Many integer
load instructions have an update form, in which rA is updated with the generated effective address. For these
forms, if rA
≠ 0 and rA ≠ rD (otherwise invalid), the EA is placed into rA and the memory element (byte, half
word, or word) addressed by the EA is loaded into rD. Note that the PowerPC Architecture defines load with
update instructions with operand rA = 0 or rA = rD as invalid forms.
Table 2-18 summarizes the integer load instructions.
Table 2-18. Integer Load Instructions (Page 1 of 2)
Name Mnemonic Syntax
Load Byte and Zero lbz rD,d(rA)
Load Byte and Zero Indexed lbzx rD,rA,rB
Load Byte and Zero with Update lbzu rD,d(rA)