IBM POWERPC 750GL - Manual (Page 296)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Bus Interface Operation
Page 296 of 377
gx_08.fm.(1.2)
March 27, 2006
8.3.2.4 Effect of Alignment in Data Transfers
Table 8-4 lists the aligned transfers that can occur on the 750GX bus. These are transfers in which the data
is aligned to an address that is an integral multiple of the size of the data. For example, Table 8-4 shows that
1-byte data is always aligned. However, for a 4-byte word to be aligned, it must be oriented on an address
that is a multiple of four.
Table 8-3. Burst Ordering—32-Bit Bus
Data Transfer
For Starting Address:
A[27–28] = 00 A[27–28] = 01 A[27–28] = 10 A[27–28] = 11
First data beat DW0-U DW1-U DW2-U DW3-U
Second data beat DW0-L DW1-L DW2-L DW3-L
Third data beat DW1-U DW2-U DW3-U DW0-U
Fourth data beat DW1-L DW2-L DW3-L DW0-L
Fifth data beat DW2-U DW3-U DW0-U DW1-U
Sixth data beat DW2-L DW3-L DW0-L DW1-L
Seventh data beat DW3-U DW0-U DW1-U DW2-U
Eighth data beat DW3-L DW0-L DW1-L DW2-L
Note:
A[29–31] are always 0b000 for burst transfers by the 750GX.
“U” and “L” represent the upper and lower word of the double word respectively.
Table 8-4. Aligned Data Transfers (Page 1 of 2)
Transfer Size TSIZ0 TSIZ1 TSIZ2 A[29–31]
Data-Bus Byte Lane(s)
0 1 2 3 4 5 6 7
Byte
0 0 1 000 x — — — — — — —
0 0 1 001 — x — — — — — —
0 0 1 010 — — x — — — — —
0 0 1 011 — — — x — — — —
0 0 1 100 — — — — x — — —
0 0 1 101 — — — — — x — —
0 0 1 110 — — — — — — x —
0 0 1 111 — — — — — — — x
Half word
0 1 0 000 x x — — — — — —
0 1 0 010 — — x x — — — —
0 1 0 100 — — — — x x — —
0 1 0 110 — — — — — — x x
Note: The entries with an “x” indicate the byte portions of the requested operand that are read or written during a bus transaction.
The entries with a “–” are not required and are ignored during read transactions, and they are driven with undefined data during all write
transactions.