IBM POWERPC 750GL - Manual (Page 285)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_08.fm.(1.2)
March 27, 2006 Bus Interface Operation
Page 285 of 377
Data tenure:
The 750GX generates an address-only bus transfer during the execution of the dcbz instruction (and for the
dcbi, dcbf, dcbst, sync, and eieio instructions, if HID0[ABE] is enabled), which uses only the address bus
with no data transfer involved. Additionally, the 750GX retry capability provides an efficient snooping protocol
for systems with multiple memory systems (including caches) that must remain coherent.
8.2.1 Arbitration Signals
Arbitration for both address-bus and data-bus mastership is performed by a central, external arbiter and,
minimally, by the arbitration signals shown in Section 7.2.1, Address-Bus Arbitration Signals, on page 251.
Most arbiter implementations require additional signals to coordinate bus master/slave/snooping activities.
Note that address-bus busy (ABB) and data bus busy (DBB) are bidirectional signals. These signals are
inputs unless the 750GX has mastership of one or both of the respective buses. They must be connected
high through pull-up resistors so that they remain negated when no devices have control of the buses.
The following list describes the address arbitration signals:
The following list describes the data arbitration signals:
Arbitration To begin the data tenure, the 750GX arbitrates for mastership of the data bus.
Transfer After the 750GX is the data-bus master, it samples the data bus for read operations or
drives the data bus for write operations. The data parity and data-parity error signals
ensure the integrity of the data transfer.
Termination Data termination signals are required after each data beat in a data transfer. Note that in a
single-beat transaction, the data termination signals also indicate the end of the tenure.
However, in burst accesses, the data termination signals apply to individual beats and indi-
cate the end of the tenure only after the final data beat.
BR (bus request) Assertion indicates that the 750GX is requesting mastership of the address bus.
BG (bus grant) Assertion indicates that the 750GX might, with the proper qualification, assume
mastership of the address bus. A qualified bus grant occurs when BG is asserted
and ABB and address retry (ARTRY) are negated.
If the 750GX is parked, BR need not be asserted for the qualified bus grant.
ABB (address bus
busy) Assertion by the 750GX indicates that the 750GX is the address-bus master.
DBG (data-bus grant) Indicates that the 750GX might, with the proper qualification, assume mastership of
the data bus. A qualified data-bus grant occurs when DBG is asserted while DBB,
date retry (DRTRY), and ARTRY are negated.
The ARTRY signal is driven from the bus and is only for the address-bus tenure
associated with the current data-bus tenure (that is, not from another address
tenure).