IBM POWERPC 750GL - Manual (Page 28)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
PowerPC 750GX Overview
Page 28 of 377
gx_01.fm.(1.2)
March 27,2006
• TLBs are hardware-reloadable (the page table search is performed by hardware).
• Bus interface features:
– Enhanced 60x bus that pipelines back-to-back reads to a depth of four. A dedicated snoop queue that
allows snoop copybacks to also pipeline with up to the four maximum reads. Enveloped write trans-
actions supported with the assertion of DBWO.
– Selectable bus-to-core clock frequency ratios of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x,
7.5x, 8x, 8.5x, 9x, 9.5x, 10x, 11x, 12x, 13x, 14x, 15x, 16x, 17x, 18x, 19x, and 20x supported (2x, 2.5x,
3x, and 3.5x not supported with bus pipelining enabled).
– A 64-bit, split-transaction external data bus with burst transfers.
– Support for address pipelining and limited out-of-order bus transactions.
– 8-word reload buffer for the L1 data cache.
– Single-entry instruction fetch queue.
– 2-entry L2 cache castout queue.
– No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant. This allows the forward-
ing of data during load operations to the internal core one bus cycle sooner than if the use of DRTRY
is enabled.
– Selectable I/O interface voltages of 1.8 V, 2.5 V, or 3.3 V
• Multiprocessing support features:
– Hardware-enforced, 3-state cache-coherency protocol (MEI) for data cache.
– Load/store with reservation instruction pair for atomic memory references, semaphores, and other
multiprocessor operations.
• Power and thermal management:
– Three static modes, doze, nap, and sleep, progressively reduce power dissipation:
• Doze—All the functional units are disabled except for the Time Base/Decrementer Registers and
the bus snooping logic.
• Nap—The nap mode further reduces power consumption by disabling bus snooping, leaving only
the Time Base Register and the PLL in a powered state.
• Sleep—All internal functional units are disabled, after which external system logic can disable the
PLL and SYSCLK.
– Software-controllable thermal management. Thermal management is performed through the use of
three supervisor-level registers and a 750GX-specific thermal-management exception.
– Software-controlled frequency switching (dual PLL mode) to allow toggling between minimum and
maximum frequencies to manage power consumption based on computational load.
– Instruction-cache throttling provides control to slow instruction fetching to limit power consumption.
• Hardware-assist features for fault-tolerant systems including L2 ECC correction, parity checking on inter-
nal arrays, and dual-processor lockstep operation.
• Performance monitor can be used to help debug system designs and improve software efficiency.
• In-system testability and debugging features through Joint Test Action Group (JTAG) boundary-scan
capability.