IBM POWERPC 750GL - Manual (Page 207)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_05.fm.(1.2)
March 27, 2006 Memory Management
Page 207 of 377
5.4.6 Page Table Updates
When TLBs are implemented (as in the 750GX), they are defined as noncoherent caches of the page tables.
TLB entries must be flushed explicitly with the TLB invalidate entry instruction (tlbie) whenever the corre-
sponding PTE is modified. As the 750GX is intended primarily for uniprocessor environments, it does not
provide coherency of TLBs between multiple processors. If the 750GX is used in a multiprocessor environ-
ment where TLB coherency is required, all synchronization must be implemented in software.
Processors can write referenced and changed bits with unsynchronized, atomic byte store operations. Note
that the valid (V), R, and C bits each reside in a distinct byte of a PTE. Therefore, extreme care must be taken
to use byte writes when updating only one of these bits.
Explicitly altering certain MSR bits (using the mtmsr instruction), or explicitly altering PTEs, or certain system
registers, can have the side effect of changing the effective or physical addresses from which the current
instruction stream is being fetched. This kind of side effect is defined as an implicit branch. Implicit branches
are not supported, and an attempt to perform one causes boundedly-undefined results. Therefore, PTEs
must not be changed in a manner that causes an implicit branch.
Chapter 2, “PowerPC Register Set” in the PowerPC Microprocessor Family: The Programming Environments
Manual
lists the possible implicit branch conditions that can occur when system registers and MSR bits are
changed.
5.4.7 Segment Register Updates
Synchronization requirements for using the Move-to Segment Register instructions are described in
“Synchronization Requirements for Special Registers and for Lookaside Buffers” in Chapter 2, “PowerPC
Register Set” in the PowerPC Microprocessor Family: The Programming Environments Manual.