IBM POWERPC 750GL - Manual (Page 278)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Signal Descriptions
Page 278 of 377
gx_07.fm.(1.2)
March 27, 2006
7.2.15.4 PLL Range (PLL_RNG[0:1])—Input
7.2.16 Power and Ground Signals
The 750GX provides the following connections for power and ground:
• V
DD
—The V
DD
signals provide the supply voltage connection for the processor core.
• OV
DD
—The OV
DD
signals provide the supply voltage connection for the system interface drivers.
• AV
DD
—The AV
DD
power signal provides power to the clock generation phase-locked loop. See the
PowerPC 750GX Datasheet for information on how to use this signal.
• GND and OGND—The GND and OGND signals provide the connection for grounding the 750GX. On the
750GX, there is no electrical distinction between the GND and OGND signals.
State Asserted/
Negated Configures the PLL operating-frequency range. Internal core clock
frequency must be within the specified range.
Timing Asserted/
Negated Must remain stable during normal operation; should only be changed during
the assertion of HRESET. These bits are readable through bits PRE[5:6] in
the HID1.