IBM POWERPC 750GL - Manual (Page 166)

User’s Manual
IBM PowerPC 750GX and GL RISC Microprocessor
Exceptions
Page 166 of 377
gx_04.fm.(1.2)
March 27, 2006
Table 4-7. Settings Caused by Hard Reset
Register Setting
BATs Unknown
Cache, instruction
cache, and data
cache
All blocks are unchanged from before
HRESET.
CR All zeros
CTR 00000000
DABR
Breakpoint is disabled.
Address is unknown.
DAR 00000000
DEC FFFFFFFF
DSISR 00000000
FPRs Unknown
FPSCR 00000000
GPRs Unknown
HID0 00000000
HID1 00000000
IABR All zeros (break point disabled)
ICTC 00000000
L2CR 00000000
LR 00000000
MMCRn 00000000
MSR 00000040 (only IP set)
PMCn Unknown
PVR See the PowerPC 750GX Datasheet
Reservation
Address
Unknown (reservation flag
-cleared)
SDR1 00000000
SPRGs 00000000
SRR0 00000000
SRR1 00000000
SRs Unknown
Tag directory,
instruction cache,
and data cache
All entries are marked invalid, all LRU bits
are set to zero, and caches are disabled.
TBL 00000000
TBU 00000000
THRMn 00000000
TLBs Unknown
UMMCRn 00000000
UPMCn 00000000
USIA 00000000
XER 00000000
Register Setting