IBM POWERPC 750GL - Manual (Page 273)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_07.fm.(1.2)
March 27, 2006 Signal Descriptions
Page 273 of 377
7.2.11 Processor Status Signals
Processor status signals indicate the state of the processor. They include the memory reservation signal,
machine quiesce control signals, time-base enable signal, and TLB Invalidate Synchronize (TLBISYNC)
signal.
7.2.11.1 Quiescent Request (QREQ)—Output
7.2.11.2 Quiescent Acknowledge (QACK)—Input
7.2.11.3 Reservation (RSRV)—Output
State Asserted Indicates that the 750GX is requesting all bus activity normally required to be
snooped to terminate or to pause so the 750GX can enter a quiescent (low
power) state. When the 750GX has entered a quiescent state, it no longer
snoops bus activity. See Chapter 10, Power and Thermal Management, on
page 335.
Negated Indicates that the 750GX is not making a request to enter the quiescent
state.
Timing Assertion/
Negation Might occur on any cycle. QREQ will remain asserted for the duration of the
quiescent state.
State Asserted Indicates that all bus activity has terminated or paused, and that the 750GX
might enter nap or sleep mode.
Negated Indicates that the 750GX cannot enter nap or sleep mode, or that it must
return to doze mode from nap mode in order to snoop.
Timing Assertion/
Negation May occur on any cycle following the assertion of QREQ. Must be negated
for at least eight bus cycles prior to performing any snoop cycles to ensure
that the 750GX has returned to doze mode from nap mode.
Start-Up See Table 7-6, Summary of Mode Select Signals, on page 274 for a descrip-
tion of the start-up function.
State Asserted/
Negated Represents the state of the internal reservation coherency bit used by the
lwarx and stwcx. instructions. See Section 8.7.1, Support for the lwarx and
stwcx. Instruction Pair, on page 319.
Timing Assertion/
Negation Might occur on any cycle. Will occur immediately following a transition of the
reservation coherency bit.