IBM POWERPC 750GL - Manual (Page 359)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_11.fm.(1.2)
March 27, 2006 Performance Monitor and System Related Features
Page 359 of 377
11.8 Resets
The 750GX supports two types of resets: a hard and a soft reset.
11.8.1 Hard Reset
The hard reset is triggered by the assertion of the hard reset pin, HRESET. The HRESET pin is asserted by
several sources:
• System power-on reset
• System reset from a panel switch
• RISCWatch
The duration of HRESET assertion depends on two factors: phase-locked loop (PLL) lock time (as specified
in the 750GX datasheet) and internal processor state initialization time. During a hard reset, the internal
latches are scanned with zeros for initialization which requires a minimum of 255 CPU clocks. A power-on
reset (POR) requires that both HRESET and TRST be active. HRESET must be active for the duration that
includes the PLL lock time plus the 255 CPU clocks for initialization. POR also requires that the test access
port (TAP) controller enter the test-logic-reset state by applying TRST.
For a hard reset to recover from a hardware problem, like a checkstop, only 255 bus clock cycles are neces-
sary to initialize the state of the processor provided the PLL remains locked.
During hard reset, all off-chip drivers will be tristated. After removal of HRESET, the processor will vector to
the system reset interrupt routine at 0xFFF00100 with MSR[IP] set high.
During HRESET, the latches dedicated to JTAG functions are not initialized. The JTAG reset signal, TRST,
resets the dedicated JTAG logic. This is in compliance with the IEEE 1149.1a-1993 standard, which prohibits
the chip reset from resetting the JTAG logic. The RISCWatch can stop the processor shortly after the SRL0
scan sequence during a hard reset, by issuing a COP force freeze command. This allows complete control of
the processor by the RISCWatch from a hard reset.
11.8.2 Soft Reset
The processor executes a system reset interrupt if the SRESET signal is asserted. Unlike a hard reset, the
latches are not initialized and the output of the MSR[IP] bit is not modified. Therefore, the system reset inter-
rupt vector address depends on the MSR[IP] bit setting prior to the assertion of SRESET. The SRESET
signal must be asserted for a minimum of two bus clocks.