2 750gx microprocessor features, Figure 1-1, 750gx microprocessor block diagram – IBM POWERPC 750GL User Manual

Page 25

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User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

gx_01.fm.(1.2)
March 27,2006

PowerPC 750GX Overview

Page 25 of 377

1.2 750GX Microprocessor Features

This section lists features of the 750GX. The interrelationship of these features is shown in Figure 1-1 on
page 25.

Major features of 750GX are:

• High-performance, superscalar microprocessor.

– As many as four instructions can be fetched from the instruction cache per clock cycle.
– As many as two instructions can be dispatched and completed per clock.
– As many as six instructions can execute per clock (including two integer instructions).
– Single-clock-cycle execution for most instructions.

• Six independent execution units and two register files.

– BPU featuring both static and dynamic branch prediction.

• 64-entry (16-set, 4-way set-associative) branch target instruction cache (BTIC), a cache of

branch instructions that have been encountered in branch/loop code sequences. If a target
instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be

Figure 1-1. 750GX Microprocessor Block Diagram

+

+

Ifetch

Branch Processing

BTIC

64 Entries

+ x ÷

FPSCR

FPSCR

CTR

LR

BHT

Data MMU

Instruction MMU

PA

EA

+ x ÷

Instruction Control Unit

Unit

Instruction Queue

(6 Words)

2 Instructions

Reservation Station

Reservation Station

Reservation Station

Integer Unit 1

System Register

Unit

Dispatch Unit

64-Bit
(2 Instructions)

SRs

ITLB

(Shadow)

IBAT

Array

32-KB

I Cache

Tags

128-Bit

(4 Instructions)

32-Bit

Floating-Point

Unit

Rename Buffers

(6)

FPR File

32-Bit

64-Bit

Reservation Station

(2 Entry)

Load/Store Unit

(EA Calculation)

Store Queue

GPR File

Rename Buffers

(6)

32-Bit

SRs

(Original)

DTLB

DBAT

Array

Completion Unit

Reorder Buffer

(6 Entry)

60x Bus Interface Unit

Instruction Fetch Queue

L1 Castout Queue

Data Load Queue

L2 Cache

32-Bit Address Bus

64-Bit Data Bus

Integer Unit 2

L2CR

1 MB

SRAM

Tags

32-KB

D Cache

Reservation Station

L2 Tag

(2 Entry)

64-Bit

256-Bit

60x Bus

256-Bit

64-Bit

64-Bit

64-Bit

Additional Features:

Time Base Cntr/
Decrementer

Clock Multiplier

JTAG/COP Interface

Thermal/Power
Management

Performance Monitor

Interrupt Logic

CR

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