IBM POWERPC 750GL User Manual
Page 358
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Performance Monitor and System Related Features
Page 358 of 377
gx_11.fm.(1.2)
March 27, 2006
• Internal registers (such as the general-purpose, floating-point, and processor version registers)
• Data cache
• Instruction cache
• L2 cache
• L2 tag
• Data tag
• Instruction tag
• Data translation lookaside buffer (TLB)
• Data Segment Registers
• Instruction TLB
• Instruction Segment Registers
• Instruction Block-Address-Translation (BAT) Registers
• External memory
INTMEM will allow reading and writing the above arrays while accessing a chain shorter than the LSRL.
INTMEM is a proper subset of the LSRL (Long Shift Register Latch).
The scan chains for the 750GX are shown Figure 11-1. The 750GX does support the optional test reset
(TRST) pin.
Figure 11-1. 750GX IEEE 1149.1a-1993/COP Organization
Boundary-Scan Registers
Long SRL Scan Chain
Exmem Scan Chain
JTAG/COP Instruction Register
Bypass Register
TDI
TDO
TAP Controller
TMS
TCK
TRST
Controller
JTAG/COP
OCD
Run_N counter
COP_PVR
Intmem Scan Chain