IBM POWERPC 750GL - Manual (Page 217)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_06.fm.(1.2)
March 27, 2006 Instruction Timing
Page 217 of 377
6.3.2.1 Cache Arbitration
When the instruction fetcher requests instructions from the instruction cache, two things might happen. If the
instruction cache is idle and the requested instructions are present, they are provided on the next clock cycle.
However, if the instruction cache is busy due to a cache-line-reload operation, instructions cannot be fetched
until that operation completes.
6.3.2.2 Cache Hit
If the instruction fetch hits the instruction cache, it takes only one clock cycle after the request for as many as
four instructions to enter the instruction queue. Note that the cache is not blocked to internal accesses while a
cache reload completes (hits under misses). The critical double word is written simultaneously to the cache
and forwarded to the requesting unit, minimizing stalls due to load delays.
Figure 6-4 on page 218 shows the paths taken by instructions.