IBM POWERPC 750GL - Manual (Page 366)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Acronyms and Abbreviations
Page 366 of 377
gx_acronyms.fm.(1.2)
March 27, 2006
FPR Floating Point Register
FPSCR Floating-Point Status and Control Register
FPU floating-point unit
GPR General Purpose Register
HIDn Hardware-Implementation-Dependent Register
IABR Instruction Address Breakpoint Register
IBAT instruction BAT
ICTC Instruction Cache Throttling Control Register
IEEE Institute for Electrical and Electronics Engineers
IMMU instruction MMU
IQ instruction queue
ITLB instruction translation lookaside buffer
IU integer unit
JTAG Joint Test Action Group
L2 secondary cache (level 2 cache)
L2CR L2 Cache Control Register
LIFO last-in-first-out
LR lInk Register
LRU least recently used
LSb least-significant bit
LSB least-significant byte
LSU load/store unit
MEI modified/exclusive/invalid
MESI modified/exclusive/shared/invalid—cache-coherency protocol
MMCRn Monitor Mode Control Registers
MMU memory management unit
MSb most-significant bit
MSB most-significant byte
MSR Machine State Register