IBM POWERPC 750GL - Manual (Page 17)

User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
750gx_umLOT.fm.(1.2)
March 27, 2006 List of Tables
Page 17 of 377
Table 5-7. Table-Search Operations to Update History Bits—TLB Hit Case ........................................ 197
Table 5-8. Model for Guaranteed R and C Bit Settings ......................................................................... 198
Table 6-1. Notation Conventions for Instruction Timing ........................................................................ 214
Table 6-2. Performance Effects of Memory Operand Placement .......................................................... 233
Table 6-3. TLB Miss Latencies .............................................................................................................. 236
Table 6-4. Branch Instructions .............................................................................................................. 238
Table 6-5. System-Register Instructions ............................................................................................... 238
Table 6-6. Condition Register Logical Instructions ................................................................................ 240
Table 6-7. Integer Instructions ............................................................................................................... 240
Table 6-8. Floating-Point Instructions .................................................................................................... 242
Table 6-9. Load-and-Store Instructions ................................................................................................. 244
Table 7-1. Transfer Type Encodings for PowerPC 750GX Bus Master ................................................ 256
Table 7-2. PowerPC 750GX Snoop Hit Response ................................................................................ 257
Table 7-3. Data-Transfer Size ............................................................................................................... 259
Table 7-4. Data-Bus Lane Assignments ................................................................................................ 266
Table 7-5. DP[0–7] Signal Assignments ................................................................................................ 267
Table 7-6. Summary of Mode Select Signals ........................................................................................ 274
Table 7-7. Bus Voltage Selection Settings ............................................................................................ 275
Table 7-8. IEEE Interface Pin Descriptions ........................................................................................... 275
Table 8-1. Transfer Size Signal Encodings ........................................................................................... 294
Table 8-2. Burst Ordering—64-Bit Bus .................................................................................................. 295
Table 8-3. Burst Ordering—32-Bit Bus .................................................................................................. 296
Table 8-4. Aligned Data Transfers ........................................................................................................ 296
Table 8-5. Misaligned Data Transfers (4-Byte Examples) ..................................................................... 298
Table 8-6. Aligned Data Transfers (32-Bit Bus Mode) .......................................................................... 298
Table 8-7. Misaligned 32-Bit Data-Bus Transfer (4-Byte Examples) ..................................................... 299
Table 9-1. Interpretation of LRU Bits ..................................................................................................... 324
Table 9-2. Modification of LRU Bits ....................................................................................................... 325
Table 9-3. Effect of Locked Ways on LRU Interpretation ...................................................................... 325
Table 10-1. 750GX Microprocessor Programmable Power Modes ......................................................... 336
Table 10-2. HID0 Power Saving Mode Bit Settings ................................................................................. 337
Table 10-3. Valid THRM1 and THRM2 Bit Settings ................................................................................ 345
Table 10-4. ICTC Bit Field Settings ......................................................................................................... 348
Table 11-1. Performance Monitor SPRs ................................................................................................. 350
Table 11-2. PMC1 Events—MMCR0[19:25] Select Encodings ............................................................... 352
Table 11-3. PMC2 Events—MMCR0[26:31] Select Encodings ............................................................... 352
Table 11-4. PMC3 Events—MMCR1[0:4] Select Encodings ................................................................... 353
Table 11-5. PMC4 Events—MMCR1[5:9] Select Encodings ................................................................... 354
Table 11-6. HID0 Checkstop Control Bits ............................................................................................... 361