Document Outline

• 1 Introduction
  • 1.1 System Overview
    • 1.1.1 Component Overview
  • 1.2 Product Features
  • 1.3 Itanium™ Processor System Bus Support
  • 1.4 DRAM Interface Support
  • 1.5 I/O Support
    • 1.5.1 PXB Features
      • 1.5.2 WXB Features
      • 1.5.3 GXB Features
    • 1.6 RAS Features
    • 1.7 Other Platform Components
      • 1.7.1 I/O & Firmware Bridge (IFB)
      • 1.7.2 Programmable Interrupt Device (PID)
  • 1.8 Reference Documents
  • 1.9 Revision History
• 2 Register Descriptions
  • 2.1 Access Mechanism
  • 2.2 Access Restrictions
    • 2.2.1 Partitioning
    • 2.2.2 Register Attributes
    • 2.2.3 Reserved Bits Defined in Registers
    • 2.2.4 Reserved or Undefined Register Locations
    • 2.2.5 Default Upon Reset
    • 2.2.6 Consistency
    • 2.2.7 GART Programming Region
  • 2.3 I/O Mapped Registers
    • 2.3.1 CONFIG_ADDRESS: Configuration Address Register
    • 2.3.2 CONFIG_DATA: Configuration Data Register
  • 2.4 Error Handling Registers
    • 2.4.1 SAC
    • 2.4.2 SDC
    • 2.4.3 MAC
    • 2.4.4 PXB
    • 2.4.5 GXB
    • 2.4.6 WXB
  • 2.5 Performance Monitor Registers
    • 2.5.1 SAC
    • 2.5.2 SDC
    • 2.5.3 PXB
    • 2.5.4 GXB
    • 2.5.5 WXB
  • 2.6 Interrupt Related Registers
    • 2.6.1 SAC
    • 2.6.2 PID PCI Memory-mapped Registers
    • 2.6.3 PID Indirect Access Registers
• 3 System Architecture
  • 3.1 Coherency
    • 3.1.1 Processor Coherency
    • 3.1.2 PCI Coherency
    • 3.1.3 AGP Coherency
  • 3.2 Ordering
  • 3.3 Processor to PCI Traffic and PCI to PCI (Peer-to- Peer) Traffic
  • 3.4 WXB Arbitration
  • 3.5 Big-endian Support
  • 3.6 Indivisible Operations
    • 3.6.1 Processor Locks
    • 3.6.2 Inbound PCI Locks
    • 3.6.3 Atomic Writes
    • 3.6.4 Atomic Reads
    • 3.6.5 Locks with AGP Non-coherent Traffic
  • 3.7 Interrupt Delivery
  • 3.8 WXB PCI Hot-Plug Support
    • 3.8.1 Slot Power-up and Enable
    • 3.8.2 Slot Power-down and Disable
• 4 System Address Map
  • 4.1 Memory Map
    • 4.1.1 Compatibility Region
    • 4.1.2 Low Extended Memory Region
    • 4.1.3 Medium Extended Memory Region
    • 4.1.4 High Extended Memory (above 4G)
    • 4.1.5 Re-mapped Memory Areas
  • 4.2 I/O Address Map
  • 4.3 Devices View of the System Memory Map
  • 4.4 Legal and Illegal Address Disposition
• 5 Memory Subsystem
  • 5.1 Organization
    • 5.1.1 DIMM Types
  • 5.2 Interleaving/Configurations
    • 5.2.1 Summary of Configuration Rules
    • 5.2.2 Non-uniform Memory Configurations
  • 5.3 Bandwidth
  • 5.4 Memory Subsystem Clocking
  • 5.5 Supporting Features
    • 5.5.1 Auto Detection
    • 5.5.2 Removing a Bad Row
    • 5.5.3 Hardware Initialization
    • 5.5.4 Memory Scrubbing
• 6 Data Integrity and Error Handling
  • 6.1 Integrity
    • 6.1.1 System Bus
    • 6.1.2 DRAM
    • 6.1.3 Expander Buses
    • 6.1.4 PCI Buses
    • 6.1.5 AGP
    • 6.1.6 Private Bus between SAC and SDC
  • 6.2 Memory ECC Routing
  • 6.3 Data Poisoning
  • 6.4 Usage of First-error and Next-error
    • 6.4.1 Masked Bits
    • 6.4.2 BERR#/BINIT# Generation
    • 6.4.3 INTREQ#
    • 6.4.4 XBINIT#
    • 6.4.5 XSERR#
  • 6.5 SAC/SDC Errors
    • 6.5.1 Data ECC or Parity Errors
    • 6.5.2 System Bus Errors
    • 6.5.3 SAC to SDC Interface Errors
    • 6.5.4 SAC to MAC Interface Errors
    • 6.5.5 SDC/Memory Card Interface Errors
    • 6.5.6 SDC/System Bus Errors
    • 6.5.7 SDC Internal Errors
  • 6.6 Error Determination
    • 6.6.1 SAC Address on an Error
    • 6.6.2 SDC Logging Registers
  • 6.7 Clearing Errors
    • 6.7.1 SAC/SDC Error Clearing
  • 6.8 Multiple Errors
    • 6.8.1 SDC Multiple Errors
    • 6.8.2 SAC Multiple Errors
    • 6.8.3 Single Errors with Multiple Reporting
    • 6.8.4 Error Anomalies
  • 6.9 Data Flow Errors
  • 6.10 Error Conditions
    • 6.10.1 Table of Errors
  • 6.11 PCI Integrity
    • 6.11.1 PCI Bus Monitoring
    • 6.11.2 PXB as Master
    • 6.11.3 PXB as Target
    • 6.11.4 GXB Error Flow
  • 6.12 WXB Data Integrity and Error Handling
    • 6.12.1 Integrity
    • 6.12.2 Data Parity Poisoning
    • 6.12.3 Usage of First Error and Next Error Registers
    • 6.12.4 Error Mask Bits
    • 6.12.5 Error Steering/Signaling
    • 6.12.6 INTRQ# Interrupt
    • 6.12.7 Error Determination and Logging
    • 6.12.8 Error Conditions
• 7 AGP Subsystem
  • 7.1 Graphics Address Relocation Table (GART)
    • 7.1.1 GART Implementation
    • 7.1.2 Programming GART
    • 7.1.3 GART Implementation
    • 7.1.4 Coherency
    • 7.1.5 Interrupt Handling
  • 7.2 AGP Traffic
    • 7.2.1 Addresses Used by the Graphics Card
    • 7.2.2 Traffic Priority
    • 7.2.3 Coherency, Translation and Types of AGP Traffic
    • 7.2.4 Ordering Rules
    • 7.2.5 Processor Locks and AGP Traffic
    • 7.2.6 Address Alignment and Transfer Sizes
    • 7.2.7 PCI Semantics Traffic
  • 7.3 Bandwidth
    • 7.3.1 Inbound Read Prefetching
  • 7.4 Latency
  • 7.5 GXB Address Map
• 8 WXB Hot-Plug
  • 8.1 IHPC Configuration Registers
    • 8.1.1 Page Number List for the IHPC PCI Register Descriptions
    • 8.1.2 VID: Vendor Identification Register
    • 8.1.3 DID: Device Identification Register
    • 8.1.4 PCICMD: PCI Command Register
    • 8.1.5 PCISTS: PCI Status Register
    • 8.1.6 RID: Revision Identification Register
    • 8.1.7 CLASS: Class Register
    • 8.1.8 CLS: Cache Line Size
    • 8.1.9 MLT: Master Latency Timer Register
    • 8.1.10 HDR: Header Register
    • 8.1.11 Base Address
    • 8.1.12 SVID: Subsystem Vendor Identification
    • 8.1.13 SID: Subsystem ID
    • 8.1.14 Interrupt Line
    • 8.1.15 Interrupt Pin
    • 8.1.16 Hot-Plug Slot Identifier
    • 8.1.17 Miscellaneous Hot-Plug Configuration
    • 8.1.18 Hot-Plug Features
    • 8.1.19 Switch Change SERR Status
    • 8.1.20 Power Fault SERR Status
    • 8.1.21 Arbiter SERR Status
    • 8.1.22 Memory Access Index
    • 8.1.23 Memory Mapped Register Access Port
  • 8.2 IHPC Memory Mapped Registers
    • 8.2.1 Page Number List for IHPC Memory Mapped Register Descriptions
    • 8.2.2 Slot Enable
    • 8.2.3 Hot-Plug Miscellaneous
    • 8.2.4 LED Control
    • 8.2.5 Hot-Plug Interrupt Input and Clear
    • 8.2.6 Hot-Plug Interrupt Mask
    • 8.2.7 Serial Input Byte Data
    • 8.2.8 Serial Input Byte Pointer
    • 8.2.9 General Purpose Output
    • 8.2.10 Hot-Plug Non-interrupt Inputs
    • 8.2.11 Hot-Plug Slot Identifier
    • 8.2.12 Hot-Plug Switch Interrupt Redirect Enable
    • 8.2.13 Slot Power Control
    • 8.2.14 Extended Hot-Plug Miscellaneous
• 9 IFB Register Mapping
  • 9.1 PCI / LPC / FWH Configuration
    • 9.1.1 PCI Configuration Registers (Function 0)
  • 9.2 IDE Configuration
    • 9.2.1 PCI Configuration Registers (Function 1)
  • 9.3 Universal Serial Bus (USB) Configuration
    • 9.3.1 PCI Configuration Registers (Function 2)
  • 9.4 SMBus Controller Configuration
    • 9.4.1 SMBus Configuration Registers (Function 3)
• 10 IFB Usage Considerations
  • 10.1 Usage of 1MIN Timer in Power Management
  • 10.2 Usage of the SW SMI# Timer
  • 10.3 CD-ROM AUTO RUN Feature of the OS
  • 10.4 ACPI, SMBus, GPIO Base Address Reporting to the OS
  • 10.5 Ultra DMA Configuration
    • 10.5.1 UDMAC–Ultra DMA Control Register (IFB Function 1 PCI Configuration Offset 48h)
    • 10.5.2 UDMATIM–Ultra DMA Timing Register (IFB Function 1 PCI Configuration Offsets 4A-4Bh)
    • 10.5.3 Determining a Drive’s Transfer Rate Capabilities
    • 10.5.4 Determining a Drive’s Best Ultra DMA Capability
    • 10.5.5 Determining a Drive’s Best Multi Word DMA/Single Word DMA (Non-ultra DMA) Capability
    • 10.5.6 IFB Timing Settings
    • 10.5.7 Drive Configuration for Selected Timings
    • 10.5.8 Settings Checklist
    • 10.5.9 Example Configurations
    • 10.5.10 Ultra DMA System Software Considerations
    • 10.5.11 Additional Ultra DMA/PCI Bus Master IDE Device Driver Considerations
  • 10.6 USB Resume Enable Bit
• 11 LPC/FWH Interface Configuration
  • 11.1 PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0)
    • 11.1.1 VID–Vendor Identification Register (Function 0)
    • 11.1.2 DID–Device Identification Register (Function 0)
    • 11.1.3 PCICMD–PCI Command Register (Function 0)
    • 11.1.4 PCISTS–PCI Device Status Register (Function 0)
    • 11.1.5 RID–Revision Identification Register (Function 0)
    • 11.1.6 CLASSC–Class Code Register (Function 0)
    • 11.1.7 HEDT–Header Type Register (Function 0)
    • 11.1.8 ACPI Base Address (Function 0)
    • 11.1.9 ACPI Enable (Function 0)
    • 11.1.10 SCI IRQ Routing Control
    • 11.1.11 BIOSEN–BIOS Enable Register (Function 0)
    • 11.1.12 PIRQRC[A:D]–PIRQx Route Control Registers (Function 0)
    • 11.1.13 SerIRQC–Serial IRQ Control Register (Function 0)
    • 11.1.14 TOM–Top of Memory Register (Function 0)
    • 11.1.15 MSTAT–Miscellaneous Status Register (Function 0)
    • 11.1.16 Deterministic Latency Control Register (Function 0)
    • 11.1.17 MGPIOC–Muxed GPIO Control (Function 0)
    • 11.1.18 PDMACFG–PCI DMA Configuration Resister (Function O)
    • 11.1.19 DDMABP–Distributed DMA Slave Base Pointer Registers (Function 0)
    • 11.1.20 RTCCFG–Real Time Clock Configuration Register (Function 0)
    • 11.1.21 GPIO Base Address (Function 0)
    • 11.1.22 GPIO Enable (Function 0)
    • 11.1.23 LPC COM Decode Ranges (Function 0)
    • 11.1.24 LPC FDD/LPT Decode Ranges (Function 0)
    • 11.1.25 LPC Sound Decode Ranges (Function 0)
    • 11.1.26 LPC Generic Decode Range (Function 0)
    • 11.1.27 LPC Enables (Function 0)
  • 11.2 PCI to LPC I/O Space Registers
    • 11.2.1 DMA Registers
    • 11.2.2 Interrupt Controller Registers
    • 11.2.3 Counter/Timer Registers
    • 11.2.4 NMI Registers
    • 11.2.5 Real Time Clock Registers
    • 11.2.6 Advanced Power Management (APM) Registers
    • 11.2.7 ACPI Registers
    • 11.2.8 SMI Registers
    • 11.2.9 General Purpose I/O Registers
• 12 IDE Configuration
  • 12.1 PCI Configuration Registers (Function 1)
  • 12.2 IDE Controller Register Descriptions (PCI Function 1)
    • 12.2.1 VID–Vendor Identification Register (Function 1)
    • 12.2.2 DID–Device Identification Register (Function 1)
    • 12.2.3 PCICMD–PCI Command Register (Function 1)
    • 12.2.4 PCISTS–PCI Device Status Register (Function 1)
    • 12.2.5 CLASSC–Class Code Register (Function 1)
    • 12.2.6 MLT–Master Latency Timer Register (Function 1)
    • 12.2.7 BMIBA–Bus Master Interface Base Address Register (Function 1)
    • 12.2.8 SVID–Subsystem Vendor ID (Function 1)
    • 12.2.9 SID–Subsystem ID (Function 1)
    • 12.2.10 IDETIM–IDE Timing Register (Function 1)
    • 12.2.11 SIDETIM–Slave IDE Timing Register (Function 1)
    • 12.2.12 DMACTL–Synchronous DMA Control Register (Function 1)
    • 12.2.13 SDMATIM–Synchronous DMA Timing Register (Function 1)
  • 12.3 IDE Controller I/O Space Registers
    • 12.3.1 BMICx–Bus Master IDE Command Register (I/O)
    • 12.3.2 BMISx–Bus Master IDE Status Register (I/O)
    • 12.3.3 BMIDTPx–Bus Master IDE Descriptor Table Pointer Register (I/O)
• 13 Universal Serial Bus (USB) Configuration
  • 13.1 PCI Configuration Registers (Function 2)
  • 13.2 USB Host Controller Register Descriptions (PCI Function 2)
    • 13.2.1 VID–Vendor Identification Register (Function 2)
    • 13.2.2 DID–Device Identification Register (Function 2)
    • 13.2.3 PCICMD–PCI Command Register (Function 2)
    • 13.2.4 PCISTS–PCI Device Status Register (Function 2)
    • 13.2.5 RID–Revision Identification Register (Function 2)
    • 13.2.6 CLASSC–Class Code Register (Function 2)
    • 13.2.7 MLT–Master Latency Timer Register (Function 2)
    • 13.2.8 HEDT–Header Type Register (Function 2)
    • 13.2.9 USBBA–USB I/O Space Base Address (Function 2)
    • 13.2.10 SVID–Subsystem Vendor ID (Function 2)
    • 13.2.11 SID–Subsystem ID (Function 2)
    • 13.2.12 INTLN–Interrupt Line Register (Function 2)
    • 13.2.13 INTPN–Interrupt Pin (Function 2)
    • 13.2.14 Miscellaneous Control (Function 2)
    • 13.2.15 SBRNUM–Serial Bus Release Number (Function 2)
    • 13.2.16 LEGSUP–Legacy Support Register (Function 2)
    • 13.2.17 USBREN–USB Resume Enable
  • 13.3 USB Host Controller I/O Space Registers
    • 13.3.1 USBCMD–USB Command Register (I/O)
    • 13.3.2 USBSTS–USB Status Register (I/O)
    • 13.3.3 USBINTR–USB Interrupt Enable Register (I/O)
    • 13.3.4 FRNUM–Frame Number Register (I/O)
    • 13.3.5 FLBASEADD–Frame List Base Address Register (I/O)
    • 13.3.6 SOFMOD–Start of Frame (SOF) Modify Register (I/O)
    • 13.3.7 PORTSC–Port Status and Control Register (I/O)
• 14 SM Bus Controller Configuration
  • 14.1 SM Bus Configuration Registers (Function 3)
  • 14.2 System Management Register Descriptions
    • 14.2.1 VID–Vendor Identification Register (Function 3)
    • 14.2.2 DID–Device Identification Register (Function 3)
    • 14.2.3 PCICMD–PCI Command Register (Function 3)
    • 14.2.4 PCISTS–PCI Device Status Register (Function 3)
    • 14.2.5 RID–Revision Identification Register (Function 3)
    • 14.2.6 CLASSC–Class Code Register (Function 3)
    • 14.2.7 SMBBA–SMBus Base Address (Function 3)
    • 14.2.8 SVID–Subsystem Vendor ID (Function 3)
    • 14.2.9 SID–Subsystem ID (Function 3)
    • 14.2.10 INTLN–Interrupt Line Register (Function 3)
    • 14.2.11 INTPN–Interrupt Pin (Function 3)
    • 14.2.12 Host Configuration
    • 14.2.13 smbslvc–SMBus Slave Command (Function 3)
    • 14.2.14 smbshdw1–SMBus Slave Shadow Port 1 (Function 3)
    • 14.2.15 smbshdw2–SMBus Slave Shadow Port 2 (Function 3)
  • 14.3 SMBus I/O Space Registers
    • 14.3.1 smbhststs–SMBus Host Status Register (I/O)
    • 14.3.2 smbslvsts–SMBus Slave Status Register (I/O)
    • 14.3.3 smbhstcnt–SMBus Host Control Register (I/O)
    • 14.3.4 smbhstcmd–SMBus Host Command Register (I/O)
    • 14.3.5 smbhstadd–SMBus Host Address Register (I/O)
    • 14.3.6 smbhstdat0–SMBus Host Data 0 Register (I/O)
    • 14.3.7 smbhstdat1–SMBus Host Data 1 Register (I/O)
    • 14.3.8 smbblkdat–SMBus Block Data Register (I/O)
    • 14.3.9 smbslvcnt–SMBus Slave Control Register (I/O)
    • 14.3.10 smbslvdat–SMBus Slave Data Register (I/O)
• 15 PCI/LPC Bridge Description
  • 15.1 PCI Interface
    • 15.1.1 Transaction Termination
    • 15.1.2 Parity Support
    • 15.1.3 PCI Arbitration
  • 15.2 Interrupt Controller
    • 15.2.1 Programming the Interrupt Controller
    • 15.2.2 End of Interrupt Operation
    • 15.2.3 Modes of Operation
    • 15.2.4 Cascade Mode
    • 15.2.5 Edge and Level Triggered Mode
    • 15.2.6 Interrupt Masks
    • 15.2.7 Reading the Interrupt Controller Status
    • 15.2.8 Interrupt Steering
  • 15.3 Serial Interrupts
    • 15.3.1 Protocol
  • 15.4 Timer/Counters
    • 15.4.1 Programming the Interval Timer
  • 15.5 Real Time Clock
    • 15.5.1 RTC Registers and RAM
    • 15.5.2 RTC Update Cycle
    • 15.5.3 RTC Interrupts
    • 15.5.4 Lockable RAM Ranges
• 16 IFB Power Management
  • 16.1 Overview
  • 16.2 IFB Power Planes
    • 16.2.1 Power Plane Descriptions
    • 16.2.2 SMI# Generation
    • 16.2.3 SCI Generation
    • 16.2.4 Sleep States
    • 16.2.5 ACPI Bits Not Implemented by IFB
    • 16.2.6 Entry/Exit for the S4 and S5 States
  • 16.3 Handling of Power Failures in IFB