Document Outline

• TABLE OF CONTENTS
• SECTION 1: Overview
• SECTION 2: Architecture
  • 2.1 Instruction Decoding
  • 2.2 Register Space
  • 2.3 Memory Types
    • 2.3.1 Flash Memory
    • 2.3.2 SRAM Memory
    • 2.3.3 Utility ROM
    • 2.3.4 Stack Memory
  • 2.4 Program and Data Memory Mapping and Access
    • 2.4.1 Program Memory Access
    • 2.4.2 Program Memory Mapping
    • 2.4.3 Data Memory Access
      • 2.4.3.1 Data Pointers
      • 2.4.3.2 Frame Pointer
    • 2.4.4 Data Memory Mapping
      • 2.4.4.1 Memory Map When Executing from Flash Memory
      • 2.4.4.2 Memory Map When Executing from Utility ROM
      • 2.4.4.3 Memory Map When Executing from SRAM
  • 2.5 Data Alignment
  • 2.6 Reset Conditions
    • 2.6.1 Power-On/Brownout Reset
    • 2.6.2 Watchdog Timer Reset
    • 2.6.3 External Reset
    • 2.6.4 Internal System Resets
  • 2.7 Clock Generation
  • 2.8 Power Modes
• SECTION 3: System Register Descriptions
  • 3.1 System Register Bit Descriptions
    • 3.1.1 Accumulator Pointer Register (AP, 8h[0h])
    • 3.1.2 Accumulator Pointer Control Register (APC, 8h[1h])
    • 3.1.3 Processor Status Flags Register (PSF, 8h[4h])
    • 3.1.4 Interrupt and Control Register (IC, 8h[5h])
    • 3.1.5 Interrupt Mask Register (IMR, 8h[6h])
    • 3.1.6 System Control Register (SC, 8h[8h])
    • 3.1.7 Interrupt Identification Register (IIR, 8h[Bh])
    • 3.1.8 System Clock Control Register (CKCN, 8h[Eh])
    • 3.1.9 Watchdog Control Register (WDCN, 8h[Fh])
    • 3.1.10 Accumulator n Register (A[n], 9h[nh])
    • 3.1.11 Prefix Register (PFX[n], Bh[n])
    • 3.1.12 Instruction Pointer Register (IP, Ch[0h])
    • 3.1.13 Stack Pointer Register (SP, Dh[1h])
    • 3.1.14 Interrupt Vector Register (IV, Dh[2h])
    • 3.1.15 Loop Counter 0 Register (LC[0], Dh[6h])
    • 3.1.16 Loop Counter 1 Register (LC[1], Dh[7h])
    • 3.1.17 Frame Pointer Offset Register (OFFS, Eh[3h])
    • 3.1.18 Data Pointer Control Register (DPC, Eh[4h])
    • 3.1.19 General Register (GR, Eh[5h])
    • 3.1.20 General Register Low Byte (GRL, Eh[6h])
    • 3.1.21 Frame Pointer Base Register (BP, Eh[7h])
    • 3.1.22 General Register Byte-Swapped (GRS, Eh[8h])
    • 3.1.23 General Register High Byte (GRH, Eh[9h])
    • 3.1.24 General Register Sign Extended Low Byte (GRXL, Eh[Ah])
    • 3.1.25 Frame Pointer Register (FP, Eh[Bh])
    • 3.1.26 Data Pointer 0 Register (DP[0], Fh[3h])
    • 3.1.27 Data Pointer 1 Register (DP[1], Fh[7h])
• SECTION 4: Peripheral Register Modules
• SECTION 5: Interrupts
  • 5.1 Servicing Interrupts
  • 5.2 Module Interrupt Identification Registers
    • 5.2.1 Peripheral Module 0 Interrupt Identification Register (MIIR0, M0[03h])
    • 5.2.2 Peripheral Module 1 Interrupt Identification Register (MIIR1, M1[04h])
    • 5.2.3 Peripheral Module 2 Interrupt Identification Register (MIIR2, M2[03h])
    • 5.2.4 Peripheral Module 3 Interrupt Identification Register (MIIR3, M3[10h])
    • 5.2.5 Peripheral Module 4 Interrupt Identification Register (MIIR4, M4[10h])
    • 5.2.6 Peripheral Module 5 Interrupt Identification Register (MIIR5, M5[18h])
  • 5.3 Interrupt System Operation
    • 5.3.1 Synchronous vs. Asynchronous Interrupt Sources
    • 5.3.2 Interrupt Prioritization by Software
    • 5.3.3 Interrupt Exception Window
• SECTION 6: Analog-to-Digital Converter (ADC)
  • 6.1 Detailed Description
    • 6.1.1 Conversion Modes
    • 6.1.2 Conversion Sequencing
    • 6.1.3 ADC Conversion Time
    • 6.1.4 ADC Data Reading
    • 6.1.5 ADC Interrupts
    • 6.1.6 Using an External Reference
    • 6.1.7 Stop Mode Operation
  • 6.2 ADC Register Descriptions
    • 6.2.1 ADC Control Register (ADCN)
    • 6.2.2 ADC Status Register (ADST)
    • 6.2.3 ADC Address Register (ADADDR)
    • 6.2.4 ADC Data and Configuration Register (ADDATA)
      • 6.2.4.1 ADC Configuration Register (ADDATA when ADCFG = 1)
      • 6.2.4.2 ADC Data Buffer (ADDATA when ADCFG = 0)
    • 6.2.5 External Temperature Slope Control Register (ETS)
    • 6.2.6 ADC External Temperature Offset Register (TOEX)
    • 6.2.7 ADC Voltage Offset Register (ADVOFF)
    • 6.2.8 ADC Voltage Scale Trim Registers (ADCG1 and ADCG5)
  • 6.3 ADC Code Examples
    • 6.3.1 One Sequence of Four Temperature and Voltage Conversions
    • 6.3.2 Continuous Conversion of 16 Samples
• SECTION 7: I2C-Compatible Slave Interface
  • 7.1 Detailed Description
    • 7.1.1 Default Operation
    • 7.1.2 Slave Address
    • 7.1.3 I2C START Detection
    • 7.1.4 I2C STOP Detection
    • 7.1.5 Slave Address Matching
    • 7.1.6 Transmitting Data
    • 7.1.7 Receiving Data
    • 7.1.8 Clock Stretching
    • 7.1.9 SMBus Timeout
    • 7.1.10 Resetting the I2C Slave Controller
    • 7.1.11 Operation as a Master
    • 7.1.12 GPIO
  • 7.2 I2C Slave Controller Register Descriptions
    • 7.2.1 I2C Slave Control Register (I2CCN_S)
    • 7.2.2 I2C Slave Status Register (I2CST_S)
    • 7.2.3 I2C Slave Interrupt Enable Register (I2CIE_S)
    • 7.2.4 I2C Slave Address Register (I2CSLA_S)
    • 7.2.5 I2C Slave Data Buffer Register (I2CBUF_S)
    • 7.2.6 SMBus Mode Selection Register (SMBUS)
    • 7.2.7 I2C Slave Clock Control Register (I2CCK_S)
    • 7.2.8 I2C Slave Timeout Register (I2CTO_S)
• SECTION 8: I2C-Compatible Master Interface
  • 8.1 Detailed Description
    • 8.1.1 Description of Master I2C Interface
    • 8.1.2 Default Operation
    • 8.1.3 I2C Clock Generation
    • 8.1.4 Timeout
    • 8.1.5 Generating a START
    • 8.1.6 Generating a STOP
    • 8.1.7 Transmitting a Slave Address
    • 8.1.8 Transmitting Data
    • 8.1.9 Receiving Data
    • 8.1.10 I2C Master Clock Stretching
    • 8.1.11 Resetting the I2C Master Controller
    • 8.1.12 Operation as a Slave
    • 8.1.13 GPIO
  • 8.2 I2C Master Controller Register Descriptions
    • 8.2.1 I2C Master Control Register (I2CCN_M)
    • 8.2.2 I2C Master Status Register (I2CST_M)
    • 8.2.3 I2C Master Interrupt Enable Register (I2CIE_M)
    • 8.2.4 I2C Master Data Buffer Register (I2CBUF_M)
    • 8.2.5 I2C Master Clock Control Register (I2CCK_M)
    • 8.2.6 I2C Master Timeout Register (I2CTO_M)
    • 8.2.7 I2C Master Address Register (I2CSLA_M)
    • 8.2.8 SMBus Mode Selection Register (SMBUS)
• SECTION 9: PWM Outputs
  • 9.1 Detailed Description
    • 9.1.1 PWM Pin Mapping and GPIO Muliplexing
    • 9.1.2 PWM Operation
    • 9.1.3 Normal PWM Output Operation
    • 9.1.4 Up/Down Count PWM Output Operation
  • 9.2 PWM Output Register Descriptions
    • 9.2.1 PWM Control Register (PWMCNn)
    • 9.2.2 PWM Value Register (PWMVn)
    • 9.2.3 PWM Reload Register (PWMRn)
    • 9.2.4 PWM Compare Register (PWMCn)
    • 9.2.5 PWM Register Locations
  • 9.3 PWM Output Code Example
• SECTION 10: Fan Tachometer
  • 10.1 Fan Tachometer Detailed Description
  • 10.2 Timer/Fan Tachometer Register Descriptions
    • 10.2.1 Tachometer Control Register (TACHCNn)
    • 10.2.2 Tachometer Value Register (TACHVn)
    • 10.2.3 Tachometer Capture Register (TACHRn)
    • 10.2.3 Tachometer Register Locations
  • 10.3 Tachometer Pin and GPIO Multiplexing
  • 10.4 Tachometer Code Example
• SECTION 11: General-Purpose Input/Output (GPIO) Pins
  • 11.1 GPIO Port 1 Register Descriptions
    • 11.1.1 GPIO Direction Register Port 1 (PD1)
    • 11.1.2 GPIO Output Register Port 1 (PO1)
    • 11.1.3 GPIO Input Register for Port 1 (PI1)
  • 11.2 GPIO Port 2 Register Descriptions
    • 11.2.1 GPIO Direction Register Port 2 (PD2)
    • 11.2.2 GPIO Output Register Port 2 (PO2)
    • 11.2.3 GPIO Input Register for Port 2 (PI2)
  • 11.3 GPIO Port 6 Register Descriptions
    • 11.3.1 GPIO Direction Register Port 6 (PD6)
    • 11.3.2 GPIO Output Register Port 6 (PO6)
    • 11.3.3 GPIO Input Register for Port 6 (PI6)
    • 11.3.4 GPIO Port 6 External Interrupt Edge Select Register (EIES6)
    • 11.3.5 GPIO Port 6 External Interrupt Flag Register (EIF6)
    • 11.3.6 GPIO Port 6 External Interrupt Enable Register (EIE6)
  • 11.4 GPIO Code Example
• SECTION 12: Timer B Module
  • 12.1 Detailed Description
    • 12.1.1 Auto-Reload Mode
    • 12.1.2 Up/Down Count with Auto-Reload
    • 12.1.3 Capture Mode
    • 12.1.4 Clock Output Mode
    • 12.1.5 PWM Output Mode
      • 12.1.5.1 Up Count PWM Output Mode
      • 12.1.5.2 Up/Down Count PWM Output Mode
  • 12.2 Timer B Register Descriptions
    • 12.2.1 Timer B Control Register (TB0CN)
    • 12.2.2 Timer B Value Register (TB0V)
    • 12.2.3 Timer B Capture/Reload Register (TB0R)
    • 12.2.4 Timer B Compare Register (TB0C)
  • 12.3 Timer B Code Examples
    • 12.3.1 Auto-Reload Mode
    • 12.3.2 Clock Output Mode
    • 12.3.3 PWM Output Mode
• SECTION 13: Supply Voltage Monitor
  • 13.1 Supply Voltage Monitor Register (SVM) Descriptions
• SECTION 14: Hardware Multiplier
  • 14.1 Hardware Multiplier Organization
  • 14.2 Hardware Multiplier Controls
  • 14.3 Register Output Selection
    • 14.3.1 Signed-Unsigned Operand Selection
    • 14.3.2 Operand Count Selection
  • 14.4 Hardware Multiplier Operations
    • 14.4.1 Accessing the Multiplier
  • 14.5 Hardware Multiplier Peripheral Registers
    • 14.5.1 Multiplier Control Register (MCNT)
    • 14.5.2 Multiplier Operand A Register (MA)
    • 14.5.3 Multiplier Operand B Register (MB)
    • 14.5.4 Multiplier Accumulator 2 Register (MC2)
    • 14.5.5 Multiplier Accumulator 1 Register (MC1)
    • 14.5.6 Multiplier Accumulator 0 Register (MC0)
    • 14.5.7 Multiplier Read Register 1 (MC1R)
    • 14.5.8 Multiplier Read Register 0 (MC0R)
  • 14.6 Hardware Multiplier Examples
• SECTION 15: Watchdog Timer
  • 15.1 Watchdog Timer Description
    • 15.1.2 Watchdog Timer Interrupt Operation
    • 15.1.2 Watchdog Timer Reset Operation
    • 15.1.3 Watchdog Timer Applications
    • 15.2.4 Watchdog Timer Control Register (WDCN)
• SECTION 16: Test Access Port (TAP)
  • 16.1 TAP Controller
  • 16.2 TAP State Control
    • 16.2.1 Test-Logic-Reset
    • 16.2.2 Run-Test-Idle
    • 16.2.3 IR-Scan Sequence
    • 16.2.4 DR-Scan Sequence
  • 16.3 Communication via TAP
    • 16.3.1 TAP Communication Examples—IR-Scan and DR-Scan
• SECTION 17: In-Circuit Debug Mode
  • 17.1 Background Mode Operation
    • 17.1.1 Breakpoint Registers
      • 17.1.1.1 Breakpoint 0 Register (BP0)
      • 17.1.1.2 Breakpoint 1 Register (BP1)
      • 17.1.1.3 Breakpoint 2 Register (BP2)
      • 17.1.1.4 Breakpoint 3 Register (BP3)
      • 17.1.1.5 Breakpoint 4 Register (BP4)
      • 17.1.1.6 Breakpoint 5 Register (BP5)
    • 17.1.2 Using Breakpoints
  • 17.2 Debug Mode
    • 17.2.1 Debug Mode Commands
    • 17.2.2 Read Register Map Command Host-ROM Interaction
    • 17.2.3 Single Step Operation (Trace)
    • 17.2.4 Return
    • 17.2.5 Debug Mode Special Considerations
  • 17.3 In-Circuit Debug Peripheral Registers
    • 17.3.1 In-Circuit Debug Temp 0 Register (ICDT0, M2[18h])
    • 17.3.2 In-Circuit Debug Temp 1 Register (ICDT1, M2[19h])
    • 17.3.3 In-Circuit Debug Control Register (ICDC, M2[1Ah])
    • 17.3.4 In-Circuit Debug Flag Register (ICDF, M2[1Bh])
    • 17.3.5 In-Circuit Debug Buffer Register (ICDB, M2[1Ch])
    • 17.3.6 In-Circuit Debug Address Register (ICDA, M2[1Dh])
    • 17.3.7 In-Circuit Debug Data Register (ICDD, M2[1Eh])
• SECTION 18: In-System Programming
  • 18.1 Detailed Description
    • 18.1.1 Password Protection
    • 18.1.2 Entering JTAG Bootloader
    • 18.1.3 Entering I2C Bootloader
    • 18.1.4 I2C System Programming Buffer Register (I2C_SPB)
  • 18.2 Bootloader Operation
    • 18.2.1 JTAG Bootloader Protocol
    • 18.2.2 I2C Bootloader Protocol
  • 18.3 Bootloader Commands
    • 18.3.1 Command 00h—No Operation
    • 18.3.2 Command 01h—Exit Loader
    • 18.3.3 Command 02h—Master Erase
    • 18.3.4 Command 03h—Password Match
    • 18.3.5 Command 04h—Get Status
    • 18.3.6 Command 05h—Get Supported Commands
    • 18.3.7 Command 06h—Get Code Size
    • 18.3.8 Command 07h—Get Data Size
    • 18.3.9 Command 08h—Get Loader Version
    • 18.3.10 Command 09h—Get Utility ROM Version
    • 18.3.11 Command 0Eh—Get Device Number
    • 18.3.12 Command 10h—Load Code
    • 18.3.13 Command 11h—Load Data
    • 18.3.14 Command 20h—Dump Code
    • 18.3.15 Command 21h—Dump Data
    • 18.3.16 Command 30h—CRC Code
    • 18.3.17 Command 31h—CRC Data
    • 18.3.18 Command 40h—Verify Code
    • 18.3.19 Command 41h—Verify Data
    • 18.3.20 Command 50h—Load and Verify Code
    • 18.3.21 Command 51h—Load and Verify Data
    • 18.3.22 Command E0h—Code Page Erase
• SECTION 19: Programming
  • 19.1 Addressing Modes
  • 19.2 Prefixing Operations
  • 19.3 Reading and Writing Registers
    • 19.3.1 Loading an 8-Bit Register with an Immediate Value
    • 19.3.2 Loading a 16-Bit Register with a 16-Bit Immediate Value
    • 19.3.3 Moving Values Between Registers of the Same Size
    • 19.3.4 Moving Values Between Registers of Different Sizes
  • 19.4 Reading and Writing Register Bits
  • 19.5 Using the Arithmetic and Logic Unit
    • 19.5.1 Selecting the Active Accumulator
    • 19.5.2 Enabling Auto-Increment and Auto-Decrement
    • 19.5.3 ALU Operations Using the Active Accumulator and a Source
    • 19.5.4 ALU Operations Using Only the Active Accumulator
    • 19.5.5 ALU Bit Operations Using Only the Active Accumulator
    • 19.5.6 Example: Adding Two 4-Byte Numbers Using Auto-Increment
  • 9.6 Processor Status Flag Operations
    • 19.6.1 Sign Flag
    • 19.6.2 Zero Flag
    • 19.6.3 Equals Flag
    • 19.6.4 Carry Flag
    • 19.6.5 Overflow Flag
  • 19.7 Controlling Program Flow
    • 19.7.1 Obtaining the Next Execution Address
    • 19.7.2 Unconditional Jumps
    • 19.7.3 Conditional Jumps
    • 19.7.4 Calling Subroutines
    • 19.7.5 Looping Operations
    • 19.7.6 Conditional Returns
  • 19.8 Handling Interrupts
    • 19.8.1 Conditional Return from Interrupt
  • 19.9 Accessing the Stack
  • 19.10 Accessing Data Memory
• SECTION 20: Instruction Set Summary
• SECTION 21: Utility ROM
  • 21.1 Overview
  • 21.2 In-Application Programming Functions
    • 21.2.1 UROM_flashWrite
    • 21.2.2 UROM_flashErasePage
    • 21.2.3 UROM_flashEraseAll
  • 21.3 Data Transfer Functions
    • 21.3.1 UROM_moveDP0
    • 21.3.2 UROM_moveDP0inc
    • 21.3.3 UROM_moveDP0dec
    • 21.3.4 UROM_moveDP1
    • 21.3.5 UROM_moveDP1inc
    • 21.3.6 UROM_moveDP1dec
    • 21.3.7 UROM_moveBP
    • 21.3.8 UROM_moveBPinc
    • 21.3.9 UROM_moveBPdec
    • 21.3.10 UROM_copyBuffer
    • 21.3.11 UROM_stopMode
  • 21.4 Utility ROM Examples
    • 21.4.1 Reading Constant Word Data from Flash
    • 21.4.2 Reading Constant Byte Data from Flash (Indirect Function Call)
• REVISION HISTORY