Maxim Integrated MAX31782 - Manual (Page 127)

 MaximIntegrated 15-3
MAX31782 User’s Guide
Revision 0; 8/11
15.1WatchdogTimerDescription
When the watchdog timer is enabled, it begins counting system clock cycles . The watchdog count is reset any time
RWT is set to 1 . If the watchdog count reaches the time interval set by WD[1:0], a watchdog timeout occurs, setting the
watchdog interrupt flag (WDCN .WDIF) . A watchdog timeout also generates an interrupt and/or reset to the MAX31782 .
Table 15-1 describes the possible states of the watchdog timer .
Table15-1.WatchdogOperatingStates
15.1.2WatchdogTimerInterruptOperation
The watchdog interrupt is enabled using the enable watchdog timer interrupt (WDCN .EWDI) bit . When the timeout
occurs, the watchdog timer sets the watchdog interrupt flag bit (WDCN .WDIF), and an interrupt occurs if the interrupt
global enable (IC .IGE) and system interrupt mask (IMR .IMS) are set and an interrupt is not currently being serviced (IC .
INS = 0) . The watchdog interrupt flag must be cleared by software .
15.1.2WatchdogTimerResetOperation
To reset the MAX31782, the watchdog timer reset function must be enabled by setting the enable watchdog timer
reset (WDCN .EWT) bit . When a watchdog timeout occurs, the WDIF flag is set and an interrupt is generated if enabled .
Following the timeout, the watchdog counts an additional 512 system clock cycles . To avoid a reset, software must
either set the RWT bit or clear the EWT bit . This can occur at any time during the watchdog timer interval or the addi-
tional 512 system clock cycles after WDIF is set . At the end of the 512 system clock cycles the MAX31782 is reset .
When the reset occurs, the watchdog timer reset flag (WDCN .WTRF) automatically is set to indicate the cause of the
reset . Software must clear this bit manually .
15.1.3WatchdogTimerApplications
Using the watchdog interrupt during software development can allow the user to select ideal watchdog reset locations .
Code is first developed without enabling the watchdog interrupt or reset functions . Once the program is complete, the
watchdog interrupt function is enabled to identify the required locations in code to set the RWT bit . Incrementally adding
instructions to reset the watchdog timer prior to each address location (identified by the watchdog interrupt) allows the
code to eventually run without receiving a watchdog interrupt . At this point the watchdog timer reset can be enabled
without the potential of generating unwanted resets . At the same time the watchdog interrupt can also be disabled .
Proper use of the watchdog interrupt with the watchdog reset allows interrupt software to survey the system for errant
conditions .
When using the watchdog timer as a system monitor, the watchdog reset function should be used . If the interrupt func-
tion were used, the purpose of the watchdog would be defeated . For example, assume the system is executing errant
code prior to the watchdog interrupt . The interrupt would temporarily force the system back into control by vectoring the
CPU to the interrupt service routine . Restarting the watchdog and exiting by an RETI or RET would return the processor
to the errant code . By using the watchdog reset function, the processor is restarted from the beginning of the program
and therefore placed into a known state .
The watchdog timer is controlled by the Watchdog Timer Control register, WDCN . The WDCN register is one of the
system registers and is located in Module 8, Register 15 .
EWT EWDI WDIF ACTIONS
x x 0 No interrupt has occurred .
0 0 x Watchdog disable, clock is gated off .
0 1 1 Watchdog interrupt has occurred .
1 0 1
No interrupt has been generated . Watchdog reset occurs in 512 system clock cycles if RWT is not
set or WDIF is not cleared .
1 1 1
Watchdog interrupt has occurred . Watchdog reset occurs in 512 system clock cycles if RWT is not
set or WDIF is not cleared .