Maxim Integrated MAX31782 - Manual (Page 97)

  MaximIntegrated  11-3
MAX31782 User’s Guide
Revision 0; 8/11
From a software perspective, each of the GPIO ports (port 1, port 2, and port 6) has three special-function registers
(POp, PIp, and PDp, where p = 1, 2, or 6) . Port 6 has three additional registers that allow for GPIO interrupts from the
port . Each GPIO port is designed to provide programming flexibility for any application .
Table 11-2 lists the associ-
ated registers and their module addresses . The user should not write to any reserved bits as this can cause undesired
behavior .
Table11-1.GPIOPinsandMultiplexedFunctions
Table11-2.GPIORegisters
TCK: Test Access Port (TAP) Clock
TDI: Test Access Port (TAP) Data Input
TMS: Test Access Port (TAP) Mode Select
TDO: Test Access Port (TAP) Data Output
TBB: Timer/Counter B Input/Output B
TBA: Timer/Counter B Input/Output A
PIN NAME
PORT
INDEX
ALTERNATE
FUNCTION(S)
ALTERNATE
FUNCTIONENABLE
SPECIAL
FUNCTION
SPECIALFUNCTIONENABLE
RESET
STATE
28 PWM .0 P1 .0 — — PWM .0 PWMCN0 .PWMCR or PWMCS = 1 GPIO
26 PWM .1 P1 .1 — — PWM .1 PWMCN1 .PWMCR or PWMCS = 1 GPIO
24 PWM .2 P1 .2 — — PWM .2 PWMCN2 .PWMCR or PWMCS = 1 GPIO
20 PWM .3 P1 .3 — — PWM .3 PWMCN3 .PWMCR or PWMCS = 1 GPIO
18 PWM .4 P1 .4 — — PWM .4 PWMCN4 .PWMCR or PWMCS = 1 GPIO
16 PWM .5 P1 .5 — — PWM .5 PWMCN5 .PWMCR or PWMCS = 1 GPIO
30 TACH .0 P2 .0 TACH .0 TACHCN0 .TEXEN = 1 — — GPIO
27 TACH .1 P2 .1 TACH .1 TACHCN1 .TEXEN = 1 — — GPIO
25 TACH .2 P2 .2 TACH .2 TACHCN2 .TEXEN = 1 — — GPIO
23 TACH .3 P2 .3 TACH .3 TACHCN3 .TEXEN = 1 — — GPIO
19 TACH .4 P2 .4 TACH .4 TACHCN4 .TEXEN = 1 — — GPIO
17 TACH .5 P2 .5 TACH .5 TACHCN5 .TEXEN = 1 — — GPIO
15 MSCL P2 .6 — — MSCL I2CCN_M .I2CEN = 1 GPIO
14 MSDA P2 .7 — — MSDA I2CCN_M .I2CEN = 1 GPIO
38 P6 .0/TCK P6 .0 TCK SC .TAP = 1 — — TCK
37 P6 .1/TDI P6 .1 TDI SC .TAP = 1 — — TDI
35
P6 .2/TMS/
TBB
P6 .2
TMS,
TBB Input
SC .TAP = 1,
TB0CN .EXENB = 1
TBB Output TB0CN .TBCR or TBCS = 1 TMS
34 P6 .3/TDO P6 .3 — — TDO SC .TAP = 1 TDO
33 P6 .4/TBA P6 .4 TBA Input TB0CN .CnTB = 1 TBA Output TB0CN .CnTB = 0 and TBCN .TBOE = 1 GPIO
32 SCL P6 .6 — — SCL I2CCN_S .I2CEN = 1 SCL
31 SDA P6 .7 — — SDA I2CCN_S .I2CEN = 1 SDA
REGISTER FUNCTION PORT1 PORT2 PORT6
POp Port Output Register M0[1h] M0[0h] M1[03h]
PIp Port Input Register M0[9h] M0[8h] M1[08h]
PDp Port Direction Register M0[11h] M0[10h] M1[12h]
EIF6 Port 6 External Interrupt Flag Register — — M1[06h]
EIE6 Port 6 External Interrupt Enable Register — — M1[07h]
EIES6 Port 6 External Interrupt Edge Select Register — — M1[10h]