Table 5-1 . interrupt sources and control bits -4, Table 5-1, Table5-1.interruptsourcesandcontrolbits – Maxim Integrated MAX31782 User Manual
Page 39
MaximIntegrated 5-4
MAX31782 User’s Guide
Revision 0; 8/11
Table5-1.InterruptSourcesandControlBits
INTERRUPT
INTERRUPTFLAG
LOCALENABLEBIT
MODULE
INTERRUPT
IDENTIFICATION
BIT
INTERRUPT
IDENTIFICATION
BIT
MODULE
ENABLE
BIT
Timer B: External Trigger
TB0CN .EXFB
TB0CN .ETB
MIIR0 .TB0
IIR .II0
IMR .IM0
Timer B: Overflow
TB0CN .TFB
I
2
C Master START Interrupt
I2CST_M .I2CSRI
I2CIE_M .I2CSRIE
MIIR1 .I2CM
IIR .II1
IMR .IM1
I
2
C Master Transmit Complete Interrupt
I2CST_M .I2CTXI
I2CIE_M .I2CTXIE
I
2
C Master Receive Ready Interrupt
I2CST_M . I2CRXI
I2CIE_M .I2CRXIE
I
2
C Master Clock Stretch Interrupt
I2CST_M .I2CSTRI
I2CIE_M .I2CSTRIE
I
2
C Master Timeout Interrupt
I2CST_M .I2CTOI
I2CIE_M .I2CTOIE
I
2
C Master NACK Interrupt
I2CST_M .I2CNACKI
I2CIE_M .I2CNACKIE
I
2
C Master Receiver Overrun Interrupt
I2CST_M .I2CROI
I2CIE_M .I2CROIE
I
2
C Master STOP Interrupt
I2CST_M .I2CSPI
I2CIE_M .I2CSPIE
I
2
C Master Wake-Up Interrupt
I2CST_M .I2CSRI
I2CIE_M .I2CSRIE
MIIR1 .I2CM_WU
External Interrupt P6 .0
EIF6 .IFP6_0
EIE6 .IEP6_0
MIIR1 .P6_0
External Interrupt P6 .1
EIF6 .IFP6_1
EIE6 .IEP6_1
MIIR1 .P6_1
External Interrupt P6 .2
EIF6 .IFP6_2
EIE6 .IEP6_2
MIIR1 . P6_2
External Interrupt P6 .3
EIF6 .IFP6_3
EIE6 .IEP6_3
MIIR1 . P6_3
External Interrupt P6 .4
EIF6 .IFP6_4
EIE6 .IEP6_4
MIIR1 . P6_4
External Interrupt P6 .6
EIF6 .IFP6_6
EIE6 .IEP6_6
MIIR1 . P6_6
External Interrupt P6 .7
EIF6 .IFP6_7
EIE6 .IEP6_7
MIIR1 . P6_7
Supply Voltage Monitor Interrupt
SVM .SVMI
SVM .SVMIE
MIIR1 .SVM
I
2
C Slave START Interrupt
I2CST_S .I2CSRI
I2CIE_S .I2CSRIE
MIIR2 .I2CS
IIR .II2
IMR .IM2
I
2
C Slave Transmit Complete Interrupt
I2CST_S .I2CTXI
I2CIE_S .I2CTXIE
I
2
C Slave Receive Ready Interrupt
I2CST_S . I2CRXI
I2CIE_S .I2CRXIE
I
2
C Slave Clock Stretch Interrupt
I2CST_S .I2CSTRI
I2CIE_S .I2CSTRIE
I
2
C Slave Timeout Interrupt
I2CST_S .I2CTOI
I2CIE_S .I2CTOIE
I
2
C Slave Address Match Interrupt
I2CST_S .I2CAMI
I2CIE_S .I2CAMIE
I
2
C Slave NACK Interrupt
I2CST_S .I2CNACKI
I2CIE_S .I2CNACKIE
I
2
C Slave General Call Interrupt
I2ST_S .I2CGCI
I2CIE_S .I2CGCIE
I
2
C Slave Receiver Overrun Interrupt
I2CST_S .I2CROI
I2CIE_S .I2CROIE
I
2
C Slave STOP Interrupt
I2CST_S .I2CSPI
I2CIE_S .I2CSPIE
I
2
C Slave Wake-Up Interrupt
I2CST_S .I2CSRI
I2CIE_S .I2CSRIE
MIIR2 .I2CS_WU
ADC Data Available Interrupt
ADST .ADDAI
ADCN .ADDAIE
MIIR2 .ADC
TACH .0 Overflow
TACHCN0 .TF
TACHCN0 .TACHIE
MIIR3 .TACH0
IIR .II3
IMR .IM3
External TACH .0 Trigger
TACHCN0 .TEXF
TACH .1 Overflow
TACHCN1 .TF
TACHCN1 .TACHIE
MIIR3 .TACH1
External TACH .1 Trigger
TACHCN1 .TEXF
TACH .2 Overflow
TACHCN2 .TF
TACHCN2 .TACHIE
MIIR4 .TACH2
IIR .II4
IMR .IM4
External TACH .2 Trigger
TACHCN2 .TEXF
TACH .3 Overflow
TACHCN3 .TF
TACHCN3 .TACHIE
MIIR4 .TACH3
External TACH .3 Trigger
TACHCN3 .TEXF
TACH .4 Overflow
TACHCN4 .TF
TACHCN4 .TACHIE
MIIR5 .TACH4
IIR .II5
IMR .IM5
External TACH .4 Trigger
TACHCN4 .TEXF
TACH .5 Overflow
TACHCN5 .TF
TACHCN5 .TACHIE
MIIR5 .TACH5
External TACH .5 Trigger
TACHCN5 .TEXF
Watchdog Interrupt
WDCN .WDIF
WDCN .EWDI
N/A
IIR .IIS
IMR .IMS