Maxim Integrated MAX31782 - Manual (Page 126)

  MaximIntegrated 15-2
MAX31782 User’s Guide
Revision 0; 8/11
SECTION 15: WATCHDOG TIMER
The watchdog timer is a user-programmable clock counter that can serve as a time-base generator, an event timer, or
a system supervisor . As shown in
Figure 15-1 , the timer is driven by the main system clock and is supplied to a series
of dividers . If the watchdog interrupt and the watchdog reset are disabled (WDCN .EWDI = 0 and WDCN .EWT = 0), the
watchdog timer and its input clock are disabled . Whenever the watchdog timer is disabled, the watchdog interval timer
(per WDCN .WD[1:0] bits) and 512 clock reset counter are reset if either the interrupt or reset function is enabled . When
the watchdog timer is initially enabled, there is a one-clock to three-clock-cycle delay before it starts . The divider output
is selectable, and determines the interval between timeouts . When the timeout is reached, an interrupt flag is set, and
if enabled, an interrupt occurs . A watchdog-reset function is also provided in addition to the watchdog interrupt . The
reset and interrupt are completely discrete functions that can be acknowledged or ignored, together or separately for
various applications .
Figure 15-1. Watchdog Timer Block Diagram
SYSTEM
CLOCK
TIMEOUT INTERVAL SELECTOR
WD1
WD0
DIVIDE BY
2 12
DIVIDE BY
2 3
2 12 2 15 2 18 2 21
DIVIDE BY
2 3
WDIF
WTRF
WATCHDOG
INTERRUPT
EWT
(ENABLE WATCHDOG TIMER RESET)
EWDI
(ENABLE WATCHDOG INTERRUPT)
RESET COUNTER
512 SYSCLK DELAY
DIVIDE BY
2 3
RWT
(RESET WATCHDOG)
TIMEOUT
RESET
MAX31782