Maxim Integrated MAX31782 - Manual (Page 139)

  MaximIntegrated 17-4
MAX31782 User’s Guide
Revision 0; 8/11
Table17-2.BackgroundModeCommands(continued)
OPCODE COMMAND OPERATION
0000–0011 Read ICDA
ReaddatafromtheICDA. The contents of the ICDA register are loaded into the debug shift reg-
ister through the ICDB register for host read . This command requires two follow-on transfer cycles
with the least significant byte first .
0000–0100 Read ICDD
ReaddatafromtheICDD. The contents of the ICDD register are loaded into the debug shift reg-
ister through the ICDB register for host read . This command requires two follow-on transfer cycles
with the least significant byte first .
0000–0101 Read BP0
ReaddatafromtheBP0 .The contents of the BP0 register are loaded into the debug shift register
through the ICDB register for host read . This command requires two follow-on transfer cycles with
the least significant byte first .
0000–0110 Read BP1
ReaddatafromtheBP1. The contents of the BP1 register are loaded into the debug shift register
through the ICDB register for host read . This command requires two follow-on transfer cycles with
the least significant byte first .
0000–0111 Read BP2
ReaddatafromtheBP2. The contents of the BP2 register are loaded into the debug shift register
through the ICDB register for host read . This command requires two follow-on transfer cycles with
the least significant byte first .
0000–1000 Read BP3
ReaddatafromtheBP3. The contents of the BP3 register are loaded into the debug shift register
through the ICDB register for host read . This command requires two follow-on transfer cycles with
the least significant byte first .
0000–1001 Read BP4
ReaddatafromtheBP4. The contents of the BP4 register are loaded into the debug shift register
via the ICDB register for host read . This command requires two follow-on transfer cycles with the
least significant byte first .
0000–1010 Read BP5
ReaddatafromtheBP5. The contents of the BP5 register are loaded into the debug shift register
via the ICDB register for host read . This command requires two follow-on transfer cycles with the
least significant byte first .
0001–0001 Write ICDC
WritecontroldatatotheICDC. The contents of ICDB are loaded into the ICDC register by the
debug engine at the end of the data transfer cycle .
0001–0011 Write ICDA
WritedatatotheICDA. The contents of ICDB are loaded into the ICDA register by the debug
engine at the end of the data transfer cycles . Data is transferred with the least significant byte first .
0001–0100 Write ICDD
WritedatatotheICDD. The contents of ICDB are loaded into the ICDD register by the debug
engine at the end of data transfer cycles . Data is transferred with the least significant byte first .
0001–0101 Write BP0
WritedatatotheBP0. The contents of ICDB are loaded into the BP0 register by the debug
engine at the end of data transfer cycles . Data is transferred with the least significant byte first .
0001–0110 Write BP1
WritedatatotheBP1. The contents of ICDB are loaded into the BP1 register by the debug
engine at the end of data transfer cycles . Data is transferred with the least significant byte first .
0001–0111 Write BP2
WritedatatotheBP2. The contents of ICDB are loaded into the BP2 register by the debug
engine at the end of data transfer cycles . Data is transferred with the least significant byte first .
0001–1000 Write BP3
WritedatatotheBP3. The contents of ICDB are loaded into the BP3 register by the debug
engine at the end of data transfer cycles . Data is transferred with the least significant byte first .
0001–1001 Write BP4
WritedatatotheBP4. The contents of ICDB are loaded into the BP4 register by the debug
engine at the end of data transfer cycles . Data is transferred with the least significant byte first .
0001–1010 Write BP5
WritedatatotheBP5. The contents of ICDB are loaded into the BP5 register by the debug
engine at the end of data transfer cycles . Data is transferred with the least significant byte first .
0001–1111 Debug
Debugcommand. This command forces the debug engine into debug mode and halts the CPU
operation at the completion of the current instruction after the debug command is recognized by
the debug engine .