Document Outline

• COVER
• GENERAL
  • FUNCTION OVERVIEW
  • ORDERING INFORMATION
  • DIFFERENCES AMONG SUBSERIES PRODUCTS
  • BLOCK DIAGRAM
  • PIN CONFIGURATION [TOP VIEW]
• PIN FUNCTIONS
  • PIN FUNCTIONS OF THE µPD750008
  • PIN FUNCTIONS
    • P00-P03 [PORT0]
    • P10-P13 [PORT1]
    • P20-P23 [PORT2]
    • P30-P33 [PORT3]
    • P40-P43 [PORT4], P50-P53 [PORT5]
    • P60-P63 [PORT6], P70-P73 [PORT7]
    • P80, P81 [PORT8]
    • TI0
    • PTO0, PTO1
    • PCL
    • BUZ
    • SCK, SO/SB0, SI/SB1
    • INT4
    • INT0, INT1
    • INT2
    • KR0-KR3
    • KR4-KR7
    • X1, X2
    • XT1, XT2
    • RESET
    • V DD
    • V SS
    • IC [for the µPD750004, µPD750006, and µPD750008 only]
    • V PP [for the µPD75P0016 only]
    • MD0-MD3 [for the µPD75P0016 only]
  • PIN INPUT/OUTPUT CIRCUITS
  • CONNECTION OF UNUSED PINS
• FEATURES OF THE ARCHITECTURE AND MEMORY MAP
  • DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES
    • Data Memory Bank Structure
    • Data Memory Addressing Modes
  • GENERAL REGISTER BANK CONFIGURATION
  • MEMORY-MAPPED I/O
• NTERNAL CPU FUNCTIONS
  • Mk I MODE/Mk II MODE SWITCH FUNCTIONS
    • Differences between Mk I Mode and Mk II Mode
    • Setting of the Stack Bank Selection Register [SBS]
  • PROGRAM COUNTER [PC]
  • PROGRAM MEMORY [ROM]
  • DATA MEMORY [RAM]
    • Data Memory Configuration
    • Specification of a Data Memory Bank
  • GENERAL REGISTER
  • ACCUMULATOR
  • STACK POINTER [SP] AND STACK BANK SELECT REGISTER [SBS]
  • PROGRAM STATUS WORD [PSW]
  • BANK SELECT REGISTER [BS]
• PERIPHERAL HARDWARE FUNCTIONS
  • DIGITAL I/O PORTS
    • Types, Features, and Configurations of Digital I/O Ports
    • I/O Mode Setting
    • Digital I/O Port Manipulation Instructions
    • Digital I/O Port Operation
    • Specification of Bilt-in Pull-Up Resistors
    • I/O Timing of Digital I/O Ports
  • CLOCK GENERATOR
    • Clock Generator Configuration
    • Functions and Operations of the Clock Generator
    • System Clock and CPU Clock Setting
    • Clock Output Circuit
  • BASIC INTERVAL TIMER/WATCHDOG TIMER
    • Configuration of the Basic Interval Timer/Watchdog Timer
    • Basic Interval Timer Mode Register [BTM]
    • Watchdog Timer Enable Flag [WDTM]
    • Operation of the Basic Interval Timer
    • Operation of the Watchdog Timer
    • Other Functions
  • CLOCK TIMER
    • Configuration of the Clock Timer
    • Clock Mode Register
  • TIMER/EVENT COUNTER
    • Configuration of Timer/Event Counter
    • 8-Bit Timer/Event Counter Mode Operation
    • Notes on Timer/Event Counter Applications
  • SERIAL INTERFACE
    • Serial Interface Functions
    • Configuration of Serial Interface
    • Register Functions
    • Operation Halt Mode
    • Three-Wire Serial I/O Mode Operations
    • Two-Wire Serial I/O Mode
    • SBI Mode Operation
    • Manipulation of SCK Pin Output
  • BIT SEQUENTIAL BUFFER
• INTERRUPT AND TEST FUNCTIONS
  • CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT
  • TYPES OF INTERRUPT SOURCES AND VECTOR TABLES
  • VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS
  • INTERRUPT SEQUENCE
  • MULTIPLE INTERRUPT PROCESSING CONTROL
  • PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS
  • MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING
  • EFFECTIVE USE OF INTERRUPTS
  • INTERRUPT APPLICATIONS
  • TEST FUNCTION
    • Test Sources
    • Hardware to Control Test Functions
• STANDBY FUNCTION
  • SETTING OF STANDBY MODES AND OPERATION STATUS
  • RELEASE OF THE STANDBY MODES
  • OPERATION AFTER A STANDBY MODE IS RELEASED
  • SELECTION OF A MASK OPTION
  • APPLICATIONS OF THE STANDBY MODES
• RESET FUNCTION
• WRITING TO AND VERIFYING PROGRAM MEMORY [PROM]
  • OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY
  • WRITING TO THE PROGRAM MEMORY
  • READING THE PROGRAM MEMORY
  • SCREENING OF ONE-TIME PROM
• MASK OPTION
  • PIN
  • MASK OPTION OF STANDBY FUNCTION
  • MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK
• INSTRUCTION SET
  • UNIQUE INSTRUCTIONS
    • GETI Instruction
    • Bit Manipulation Instructions
    • String-Effect Instructions
    • Number System Conversion Instructions
    • Skip Instructions and the Number of Machine Cycles Required for a Skip
  • INSTRUCTION SET AND OPERATION
  • INSTRUCTION CODES OF EACH INSTRUCTION
  • FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS
    • Transfer Instructions
    • Table Reference Instructions
    • Bit Transfer Instructions
    • Arithmetic/Logical Instructions
    • Accumulator Manipulation Instructions
    • Increment/Decrement Instructions
    • Compare Instructions
    • Carry Flag Manipulation Instructions
    • Memory Bit Manipulation Instructions
    • Branch Instructions
    • Subroutine Stack Control Instructions
    • Interrupt Control Instructions
    • I/O Instructions
    • CPU Control Instructions
    • Special Instructions
• APPENDIX
  • FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016
  • DEVELOPMENT TOOLS
  • MASKED ROM ORDERING PROCEDURE
  • INSTRUCTION INDEX
    • D1 INSTRUCTION INDEX [BY FUNCTION]
    • D2 INSTRUCTION INDEX [ALPHABETICAL ORDER]
  • HARDWARE INDEX
    • E1 HARDWARE INDEX [ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME]
    • E2 HARDWARE INDEX [ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL]
  • REVISION HISTORY