Document Outline

• Features
• 1. Pin-out Diagram
  • 1.1 Pin Descriptions
  • 1.2 Analog and RF Pins
    • 1.2.1 Supply and Ground Pins
    • 1.2.2 RF Pins
    • 1.2.3 Crystal Oscillator Pins
    • 1.2.4 Analog Pin Summary
  • 1.3 Digital Pins
    • 1.3.1 Driver Strength Settings
    • 1.3.2 Pull-Up and Pull-Down Configuration
    • 1.3.3 Register Description
• 2. Disclaimer
• 3. Overview
• 4. General Circuit Description
• 5. Application Circuits
  • 5.1 Basic Application Schematic
  • 5.2 Extended Feature Set Application Schematic
• 6. Microcontroller Interface
  • 6.1 SPI Timing Description
  • 6.2 SPI Protocol
    • 6.2.1 Register Access Mode
    • 6.2.2 Frame Buffer Access Mode
    • 6.2.3 SRAM Access Mode
  • 6.3 Radio Transceiver Status information
    • 6.3.1 Register Description - SPI Control
  • 6.4 Radio Transceiver Identification
    • 6.4.1 Register Description - AT86RF231 Identification
  • 6.5 Sleep/Wake-up and Transmit Signal (SLP_TR)
  • 6.6 Interrupt Logic
    • 6.6.1 Overview
    • 6.6.2 Register Description
• 7. Operating Modes
  • 7.1 Basic Operating Mode
    • 7.1.1 State Control
    • 7.1.2 Basic Operating Mode Description
      • 7.1.2.1 P_ON - Power-On after VDD
      • 7.1.2.2 SLEEP - Sleep State
      • 7.1.2.3 TRX_OFF - Clock State
      • 7.1.2.4 PLL_ON - PLL State
      • 7.1.2.5 RX_ON and BUSY_RX - RX Listen and Receive State
      • 7.1.2.6 RX_ON_NOCLK - RX Listen State without CLKM
      • 7.1.2.7 BUSY_TX - Transmit State
      • 7.1.2.8 RESET State
    • 7.1.3 Interrupt Handling
    • 7.1.4 Basic Operating Mode Timing
      • 7.1.4.1 Power-on Procedure
      • 7.1.4.2 Wake-up Procedure
      • 7.1.4.3 PLL_ON and RX_ON States
      • 7.1.4.4 BUSY_TX and RX_ON States
      • 7.1.4.5 Reset Procedure
      • 7.1.4.6 State Transition Timing Summary
    • 7.1.5 Register Description
  • 7.2 Extended Operating Mode
    • 7.2.1 State Control
    • 7.2.2 Configuration
    • 7.2.3 RX_AACK_ON - Receive with Automatic ACK
      • 7.2.3.1 Description of RX_AACK Configuration Bits
      • 7.2.3.2 Configuration of IEEE Scenarios
      • 7.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios
      • 7.2.3.4 RX_AACK_NOCLK - RX_AACK_ON without CLKM
      • 7.2.3.5 Frame Filtering
      • 7.2.3.6 RX_AACK Slotted Operation - Slotted Acknowledgement
      • 7.2.3.7 RX_AACK Mode Timing
    • 7.2.4 TX_ARET_ON - Transmit with Automatic Retry and CSMA-CA Retry
    • 7.2.5 Interrupt Handling
    • 7.2.6 Register Summary
    • 7.2.7 Register Description - Control Registers
    • 7.2.8 Register Description - Address Registers
• 8. Functional Description
  • 8.1 Introduction - IEEE 802.15.4 - 2006 Frame Format
    • 8.1.1 PHY Protocol Layer Data Unit (PPDU)
      • 8.1.1.1 8.1.1.1 Synchronization Header (SHR)
      • 8.1.1.2 PHY Header (PHR)
      • 8.1.1.3 PHY Payload (PHY Service Data Unit, PSDU)
    • 8.1.2 MAC Protocol Layer Data Unit (MPDU)
      • 8.1.2.1 MAC Header (MHR) Fields
      • 8.1.2.2 Frame Control Field (FCF)
      • 8.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006
      • 8.1.2.4 Sequence Number
      • 8.1.2.5 Addressing Fields
      • 8.1.2.6 Auxiliary Security Header Field
      • 8.1.2.7 MAC Service Data Unit (MSDU)
      • 8.1.2.8 MAC Footer (MFR) Fields
  • 8.2 Frame Check Sequence (FCS)
    • 8.2.1 Overview
    • 8.2.2 CRC Calculation
    • 8.2.3 Automatic FCS generation
    • 8.2.4 Automatic FCS check
    • 8.2.5 Register Description
  • 8.3 Received Signal Strength Indicator (RSSI)
    • 8.3.1 Overview
    • 8.3.2 Reading RSSI
    • 8.3.3 Data Interpretation
    • 8.3.4 Register Description
  • 8.4 Energy Detection (ED)
    • 8.4.1 Overview
    • 8.4.2 Measurement Description
    • 8.4.3 Data Interpretation
    • 8.4.4 Interrupt Handling
    • 8.4.5 Register Description
  • 8.5 Clear Channel Assessment (CCA)
    • 8.5.1 Overview
    • 8.5.2 Configuration and Request
    • 8.5.3 Data Interpretation
    • 8.5.4 Interrupt Handling
    • 8.5.5 Measurement Time
    • 8.5.6 Register Description
  • 8.6 Link Quality Indication (LQI)
    • 8.6.1 Overview
    • 8.6.2 Request an LQI Measurement
    • 8.6.3 Data Interpretation
• 9. Module Description
  • 9.1 Receiver (RX)
    • 9.1.1 Overview
    • 9.1.2 Frame Receive Procedure
    • 9.1.3 Configuration
    • 9.1.4 Register Description
  • 9.2 Transmitter (TX)
    • 9.2.1 Overview
    • 9.2.2 Frame Transmit Procedure
    • 9.2.3 Configuration
    • 9.2.4 TX Power Ramping
    • 9.2.5 Register Description
  • 9.3 Frame Buffer
    • 9.3.1 Data Management
    • 9.3.2 User accessible Frame Content
    • 9.3.3 Interrupt Handling
  • 9.4 Voltage Regulators (AVREG, DVREG)
    • 9.4.1 Overview
    • 9.4.2 Configuration
    • 9.4.3 Data Interpretation
    • 9.4.4 Register Description
  • 9.5 Battery Monitor (BATMON)
    • 9.5.1 Overview
    • 9.5.2 Configuration
    • 9.5.3 Data Interpretation
    • 9.5.4 Interrupt Handling
    • 9.5.5 Register Description
  • 9.6 Crystal Oscillator (XOSC)
    • 9.6.1 Overview
    • 9.6.2 Integrated Oscillator Setup
    • 9.6.3 External Reference Frequency Setup
    • 9.6.4 Master Clock Signal Output (CLKM)
    • 9.6.5 Register Description
  • 9.7 Frequency Synthesizer (PLL)
    • 9.7.1 Overview
    • 9.7.2 RF Channel Selection
    • 9.7.3 Frequency Agility
    • 9.7.4 Calibration Loops
    • 9.7.5 Interrupt Handling
    • 9.7.6 Register Description
  • 9.8 Automatic Filter Tuning (FTN)
    • 9.8.1 Overview
    • 9.8.2 Register Description
• 10. Radio Transceiver Usage
  • 10.1 Frame Receive Procedure
  • 10.2 Frame Transmit Procedure
• 11. AT86RF231 Extended Feature Set
  • 11.1 Security Module (AES)
    • 11.1.1 Overview
    • 11.1.2 Security Module Preparation
    • 11.1.3 Security Key Setup
    • 11.1.4 Security Operation Modes
      • 11.1.4.1 Electronic Code Book (ECB)
      • 11.1.4.2 Cipher Block Chaining (CBC)
    • 11.1.5 Data Transfer - Fast SRAM Access
    • 11.1.6 Start of Security Operation and Status
    • 11.1.7 SRAM Register Summary
    • 11.1.8 AES SRAM Configuration Register
  • 11.2 Random Number Generator
    • 11.2.1 Overview
    • 11.2.2 Register Description
  • 11.3 High Data Rate Modes
    • 11.3.1 Overview
    • 11.3.2 High Data Rate Packet Structure
    • 11.3.3 High Data Rate Frame Buffer Access
    • 11.3.4 High Data Rate Energy Detection
    • 11.3.5 High Data Rate Mode Options
    • 11.3.6 Register Description
  • 11.4 Antenna Diversity
    • 11.4.1 Overview
    • 11.4.2 Antenna Diversity Application Example
    • 11.4.3 Antenna Diversity Sensitivity Control
    • 11.4.4 Register Description
  • 11.5 RX/TX Indicator
    • 11.5.1 Overview
    • 11.5.2 External RF-Front End Control
    • 11.5.3 Register Description
  • 11.6 RX Frame Time Stamping
    • 11.6.1 Overview
    • 11.6.2 Register Description
  • 11.7 Frame Buffer Empty Indicator
    • 11.7.1 Overview
    • 11.7.2 Register Description
  • 11.8 Dynamic Frame Buffer Protection
    • 11.8.1 Overview
    • 11.8.2 Register Description
  • 11.9 Configurable Start-Of-Frame Delimiter
    • 11.9.1 Overview
    • 11.9.2 Register Description
• 12. Electrical Characteristics
  • 12.1 Absolute Maximum Ratings
  • 12.2 Recommended Operating Range
  • 12.3 Digital Pin Characteristics
  • 12.4 Digital Interface Timing Characteristics
  • 12.5 General RF Specifications
  • 12.6 Transmitter Characteristics
  • 12.7 Receiver Characteristics
  • 12.8 Current Consumption Specifications
  • 12.9 Crystal Parameter Requirements.
• 13. Typical Characteristics
  • 13.1 Active Supply Current
    • 13.1.1 TRX_OFF state
    • 13.1.2 PLL_ON state
    • 13.1.3 RX_ON state
    • 13.1.4 TX_BUSY state
  • 13.2 State Transition Timing
• 14. Register Summary
• 15. Abbreviations
• 16. Ordering Information
• 17. Soldering Information
• 18. Package Thermal Properties
• 19. Package Drawing - 32QN2
• 20. Appendix A - Continuous Transmission Test Mode
  • 20.1 Overview
  • 20.2 Configuration
  • 20.3 Register Description
• 21. Appendix B - Errata
  • 21.1 AT86RF231 Rev.A
• References
• Table of Contents