5 interrupt handling, 6 register description, Section 9.7.5 – Rainbow Electronics AT86RF231 User Manual

Page 122

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122

8111A–AVR–05/08

AT86RF231

If the PLL operates for a long time on the same channel, e.g. more than 5 min, or the operating
temperature changes significantly, it is recommended to initiate the calibration loops manually.

Both calibration loops can be initiated manually by setting PLL_CF_START = 1 (register 0x1A,
PLL_CF) and register bit PLL_DCU_START = 1 (register 0x1B, PLL_DCU). To start the calibra-
tion the device must be in PLL_ON or RX_ON state. The completion of the center frequency
tuning is indicated by a PLL_LOCK interrupt.

Both calibration loops may be run simultaneously.

9.7.5

Interrupt Handling

Two different interrupts indicate the PLL status (refer to register 0x0F). IRQ_0 (PLL_LOCK) indi-
cates that the PLL has locked. IRQ_1 (PLL_UNLOCK) interrupt indicates an unexpected unlock
condition. A PLL_LOCK interrupt clears any preceding PLL_UNLOCK interrupt automatically
and vice versa.

A PLL_LOCK interrupt is supposed to occur in the following situations:

• State change from TRX_OFF to PLL_ON / RX_ON

• Channel change in states PLL_ON / RX_ON

Any other occurrences of PLL interrupts indicate erroneous behavior and require checking of the
actual device status.

The state transition from BUSY_TX to PLL_ON after successful transmission does not generate
an IRQ_0 (PLL_LOCK) within the settling period.

9.7.6

Register Description

Register 0x08 (PHY_CC_CCA):

This register sets the IEEE 802.15.4 - 2.4 GHz channel number

• Bit 7 - CCA_REQUEST

Refer to

Section 8.5 “Clear Channel Assessment (CCA)” on page 94

.

• Bit [6:5] - CCA_MODE

Refer to

Section 8.5 “Clear Channel Assessment (CCA)” on page 94

.

• Bit [4:0] - CHANNEL

The register bits CHANNEL define the RX/TX channel. The channel assignment is according to
IEEE 802.15.4.

Bit

7

6

5

4

3

2

1

0

+0x08

CCA_REQUEST

CCA_MODE

CHANEL

PHY_CC_CCA

Read/Write

W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

0

0

1

0

1

0

1

1

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