Rainbow Electronics AT86RF231 User Manual
Page 73
73
8111A–AVR–05/08
AT86RF231
Register 0x2C (XAH_CTRL_0):
Register 0x2C (XAH_CTRL_0) is a control register for Extended Operating Mode.
• Bit [7:4] - MAX_FRAME_RETRIES
The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to
retransmit a frame, when it was not acknowledged by the recipient, before the transaction gets
cancelled.
• Bit [3:1] - MAX_CSMA_RETRIES
MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-
CA procedure before the transaction gets cancelled. According IEEE 802.15.4 the valid range of
MAX_CSMA_RETRIES is [0, 1, …, 5].
A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without per-
forming CSMA-CA. This may especially be required for slotted acknowledgement operation.
MAX_CSMA_RETRIES = 6 is reserved.
• Bit 0 - SLOTTED_OPERATION
Using RX_AACK mode in networks operating in beacon or slotted mode, refer to IEEE 802.15.4
2006, section 5.5.1, register bit SLOTTED_OPERATION indicates that acknowledgement
frames are to be sent on back-off slot boundaries (slotted acknowledgement).
If this register bit is set the acknowledgement frame transmission has to be initiated by the
microcontroller using the rising edge of pin 11 (SLP_TR). This waiting state is signaled in sub
register TRAC_STATUS (register 0x02, TRX_STATE) with value SUCCESS_WAIT_FOR_ACK.
Register 0x2D (CSMA_SEED_0):
Bit
7
6
5
4
3
2
1
0
+0x2C
MAX_FRAME_RETRIES
MAX_CSMA_RETRIES
SLOTTED_OPERATION
XAH_CTRL_0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
1
1
1
0
0
0
Table 7-18.
Register Bit Slotted Acknowledgement Operation
Register Bit
Value
State Description
SLOTTED_OPERATION
0
The radio transceiver operates in unslotted mode. An
acknowledgment frame is automatically sent if requested.
1
Refer to
. The transmission of an
acknowledgement frame has to be controlled by the
microcontroller.
Bit
7
6
5
4
3
2
1
0
+0x2D
CSMA_SEED_0[7:0]
CSMA_SEED_0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
1
1
1
0
1
0
1
0