Rainbow Electronics AT86RF231 - Manual (Page 18)

18
8111A–AVR–05/08
AT86RF231
The SPI is based on a byte-oriented protocol and is always a bidirectional communication
between master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the
master generates eight SPI clock cycles to transfer one byte to the radio transceiver (via MOSI).
At the same time, the slave transmits one byte to the master (via MISO). When the master wants
to receive one byte of data from the slave it must also transmit one byte to the slave. All bytes
are transferred with MSB first. An SPI transaction is finished by releasing /SEL = H.
An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or
more bytes as described in
Section 6.2 “SPI Protocol” on page 19 .
/SEL = L enables the MISO output driver of the AT86RF231. The MSB of MISO is valid after t1
(see
Section 12.4 “Digital Interface Timing Characteristics” on page 157 parameter 12.4.3) and
is updated at each falling edge of SCLK. If the driver is disabled, there is no internal pull-up
resistor connected to it. Driving the appropriate signal level must be ensured by the master
device or an external pull-up resistor. Note, when both /SEL and /RST are active, the MISO out-
put driver is also enabled.
Referring to Figure 6-2 on page 17 and Figure 6-3 on page 17 MOSI is sampled at the rising
edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be
stable before and after the rising edge of SCLK as specified by t
3
and t
4
, refer to Section 12.4
“Digital Interface Timing Characteristics” on page 157 parameters 12.4.5 and 12.4.6.
This SPI operational mode is commonly known as "SPI mode 0".