Document Outline

• Features
• Disclaimer
• Pin Configuration
• Description
  • Block Diagram
  • Pin Descriptions
    • VCC
    • GND
    • Port A (PA7..PA0)
    • Port B (PB7..PB0)
    • Port C (PC7..PC0)
    • Port D (PD7..PD0)
    • Port E (PE2..PE0)
    • RESET
    • XTAL1
    • XTAL2
  • Crystal Oscillator
• Architectural Overview
  • The General Purpose Register File
    • The X-register, Yregister and Zregister
  • ALU – Arithmetic Logic Unit
  • Self-programmable Flash Program Memory
  • EEPROM Data Memory
  • SRAM Data Memory
  • Program and Data Addressing Modes
    • Register Direct, Single Register Rd
    • Register Direct, Two Registers Rd and Rr
    • I/O Direct
    • Data Direct
    • Data Indirect with Displacement
    • Data Indirect
    • Data Indirect with Pre- decrement
    • Data Indirect with Post- increment
    • Constant Addressing Using the LPM Instruction
    • Indirect Program Addressing, IJMP and ICALL
    • Relative Program Addressing, RJMP and RCALL
    • Direct Program Addressing, JMP and CALL
  • Memory Access Times and Instruction Execution Timing
  • l/O Memory
    • Status Register – SREG
    • Stack Pointer – SP
  • Reset and Interrupt Handling
    • Reset Sources
    • Power-on Reset
    • External Reset
    • Watchdog Reset
    • MCU Status Register – MCUSR
    • Interrupt Handling
    • Interrupt Response Time
    • General Interrupt Mask Register – GIMSK
    • General Interrupt Flag Register – GIFR
    • Timer/Counter Interrupt Mask Register – TIMSK
    • Timer/Counter Interrupt Flag Register – TIFR
    • External Interrupts
  • MCU Control Register – MCUCR
    • Extended MCU Control Register – EMCUCR
  • Sleep Modes
    • Idle Mode
    • Power-down Mode
    • Power-save Mode
• Timer/Counters
  • Timer/Counter Prescalers
    • Special Function IO Register – SFIOR
  • 8-bit Timer/Counters T/C0 and T/C2
    • Timer/Counter0 Control Register – TCCR0
    • Timer/Counter2 Control Register – TCCR2
    • Timer Counter0 – TCNT0
    • Timer/Counter2 – TCNT2
    • Timer/Counter0 Output Compare Register – OCR0
    • Timer/Counter2 Output Compare Register – OCR2
    • Timer/Counters 0 and 2 in PWM Mode
    • PWM Modes (Up/Down and Overflow)
    • Asynchronous Status Register – ASSR
    • Asynchronous Operation of Timer/Counter2
  • Timer/Counter1
    • Timer/Counter1 Control Register A – TCCR1A
    • Timer/Counter1 Control Register B – TCCR1B
    • Timer/Counter1 Register – TCNT1H AND TCNT1L
    • Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL
    • Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL
    • Timer/Counter1 Input Capture Register – ICR1H AND ICR1L
    • Timer/Counter1 in PWM Mode
• Watchdog Timer
  • Watchdog Timer Control Register – WDTCR
• EEPROM Read/Write Access
  • EEPROM Address Register – EEARH and EEARL
  • EEPROM Data Register – EEDR
  • EEPROM Control Register – EECR
  • Prevent EEPROM Corruption
• Serial Peripheral Interface – SPI
  • SS Pin Functionality
  • Data Modes
    • SPI Control Register – SPCR
    • SPI Status Register – SPSR
    • SPI Data Register – SPDR
• UARTs
  • Data Transmission
  • Data Reception
    • Multi-processor Communication Mode
  • UART Control
    • UART0 I/O Data Register – UDR0
    • UART1 I/O Data Register – UDR1
    • UART0 Control and Status Registers – UCSR0A
    • UART1 Control and Status Registers – UCSR1A
    • UART0 Control and Status Registers – UCSR0B
    • UART1 Control and Status Registers – UCSR1B
  • Baud Rate Generator
    • UART0 and UART1 High Byte Baud Rate Register UBRRHI
    • UART0 Baud Rate Register Low Byte – UBRR0
    • UART1 Baud Rate Register Low Byte – UBRR1
  • Double-speed Transmission
    • The Baud Rate Generator in Double UART Speed Mode
• Analog Comparator
  • Analog Comparator Control and Status Register – ACSR
• Internal Voltage Reference
  • Voltage Reference Enable Signals and Start- up Time
• Interface to External Memory
  • MCU Control Register – MCUCR
  • Extended MCU Control Register – EMCUCR
  • Using the External Memory Interface
• I/O Ports
  • Port A
    • Port A Data Register – PORTA
    • Port A Data Direction Register – DDRA
    • Port A Input Pins Address – PINA
    • Port A as General Digital I/O
    • Port A Schematics
  • Port B
    • Port B Data Register – PORTB
    • Port B Data Direction Register – DDRB
    • Port B Input Pins Address – PINB
    • Port B as General Digital I/O
    • Alternate Functions of PortB
  • Port B Schematics
  • Port C
    • Port C Data Register – PORTC
    • Port C Data Direction Register – DDRC
    • Port C Input Pins Address – PINC
    • Port C as General Digital I/O
    • Port C Schematics
  • Port D
    • Port D Data Register – PORTD
    • Port D Data Direction Register – DDRD
    • Port D Input Pins Address – PIND
    • Port D as General Digital I/O
    • Alternate Functions of Port D
    • Port D Schematics
  • Port E
    • Port E Data Register – PORTE
    • Port E Data Direction Register – DDRE
    • Port E Input Pins Address – PINE
    • Port E as General Digital I/O
    • Alternate Functions of Port E
    • Port E Schematics
• Memory Programming
  • Boot Loader Support
  • Entering the Boot Loader Program
  • Capabilities of the Boot Loader
  • Self-programming the Flash
    • Setting the Boot Loader Lock bits by SPM
    • Performing Page Erase by SPM
    • Fill the Temporary Buffer
    • Perform a Page Write
    • Addressing the FLASH during Self-programming
    • Store Program Memory Control Register – SPMCR
    • EEPROM Write Prevents Writing to SPMCR
    • Reading the Fuse and Lock bits from Software
• Program Memory Lock bits
  • Fuse bits
  • Signature Bytes
  • Programming the Flash and EEPROM
  • Parallel Programming
    • Signal Names
    • Enter Programming Mode
    • Chip Erase
    • Programming the Flash
    • Programming the EEPROM
    • Reading the Flash
    • Reading the EEPROM
    • Programming the Fuse Bits
    • Programming the Lock Bits
    • Reading the Fuse and Lock Bits
    • Reading the Signature Bytes
  • Parallel Programming Characteristics
  • Serial Downloading
    • Serial Programming Algorithm
    • Data Polling Flash
    • Data Polling EEPROM
  • Serial Programming Characteristics
• Electrical Characteristics
  • Absolute Maximum Ratings*
• DC Characteristics 
  • External Clock Drive Waveforms
  • External Data Memory Timing
• Typical Characteristics
• Register Summary
• Instruction Set Summary
• Ordering Information
• Packaging Information
  • 44A
  • 40P6
• Errata
  • ATmega161 Rev. E
• Data Sheet Change Log for ATmega161
  • Changes from Rev. 1228B-09/01 to Rev. 1228C-08/02
• Table of Contents