Document Outline

• Features
• Pin Configuration
• Description
  • Block Diagram
  • Pin Descriptions
    • VCC
    • GND
    • Port B (PB5..PB0)
    • Analog Pins
  • Internal Oscillators
• ATtiny15L Architectural Overview
  • The General Purpose Register File
  • The ALU – Arithmetic Logic Unit
  • The Flash Program Memory
  • The Program and Data Addressing Modes
    • Register Direct, Single- register Rd
    • Register Indirect
    • Register Direct, Two Registers Rd and Rr
    • I/O Direct
    • Relative Program Addressing, RJMP and RCALL
    • Constant Addressing using the LPM Instruction
  • Subroutine and Interrupt Hardware Stack
  • The EEPROM Data Memory
    • Memory Access and Instruction Execution Timing
  • I/O Memory
    • The Status Register – SREG
  • Reset and Interrupt Handling
    • ATtiny15L Reset Sources
    • Power-on Reset
    • External Reset
    • Brown-out Detection
    • Watchdog Reset
    • MCU Status Register – MCUSR
  • Internal Voltage Reference
    • Voltage Reference Enable Signals and Start-up Time
  • Interrupt Handling
    • Interrupt Response Time
    • The General Interrupt Mask Register – GIMSK
    • The General Interrupt Flag Register – GIFR
    • The Timer/Counter Interrupt Mask Register – TIMSK
    • The Timer/Counter Interrupt Flag Register – TIFR
    • External Interrupt
    • Pin Change Interrupt
    • The MCU Control Register – MCUCR
  • Sleep Modes
    • Idle Mode
    • ADC Noise Reduction Mode
    • Power-down Mode
  • Tuneable Internal RC Oscillator
    • The System Clock Oscillator Calibration Register – OSCCAL
  • Internal PLL for Fast Peripheral Clock Generation
• Timer/Counters
  • The Timer/Counter0 Prescaler
  • The Timer/Counter1 Prescaler
  • The Special Function IO Register – SFIOR
  • The 8-bit Timer/Counter0
    • The Timer/Counter0 Control Register – TCCR0
    • The Timer Counter 0 – TCNT0
  • The 8-bit Timer/Counter1
    • The Timer/Counter1 Control Register – TCCR1
    • The Timer/Counter1 – TCNT1
    • Timer/Counter1 Output Compare RegisterA – OCR1A
    • Timer/Counter1 in PWM Mode
    • Timer/Counter1 Output Compare RegisterB – OCR1B
• The Watchdog Timer
  • The Watchdog Timer Control Register – WDTCR
• EEPROM Read/Write Access
  • The EEPROM Address Register – EEAR
  • The EEPROM Data Register – EEDR
  • The EEPROM Control Register – EECR
  • Preventing EEPROM Corruption
• The Analog Comparator
  • The Analog Comparator Control and Status Register – ACSR
• The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages
  • Features
  • Operation
  • Prescaling and Conversion Timing
  • ADC Noise Canceler Function
    • The ADC Multiplexer Selection Register – ADMUX
    • The ADC Control and Status Register – ADCSR
    • The ADC Data Register – ADCL and ADCH
      • ADLAR = 0
      • ADLAR = 1
    • Scanning Multiple Channels
  • ADC Noise-canceling Techniques
  • ADC Characteristics
• I/O Port B
  • Alternative Functions of Port B
  • The Port B Data Register – PORTB
  • The Port B Data Direction Register – DDRB
  • The Port B Input Pins Address – PINB
  • PORT B as General Digital I/O
  • Alternate Functions of Port B
• Memory Programming
  • Program and Data Memory Lock Bits
  • Fuse Bits
  • Signature Bytes
  • Calibration Byte
  • Programming the Flash
  • High-voltage Serial Programming
  • High-voltage Serial Programming Algorithm
  • High-voltage Serial Programming Characteristics
  • Low-voltage Serial Downloading
    • Low-voltage Serial Programming Algorithm
    • Data Polling
  • Low-voltage Serial Programming Characteristics
• Electrical Characteristics
  • Absolute Maximum Ratings
  • DC Characteristics 
• Typical Characteristics
• ATtiny15L Register Summary
• ATtiny15L Instruction Set Summary
• Ordering Information
• Packaging Information
  • 8P3
  • 8S2
• Table of Contents