Document Outline

• FEATURES
  • General
  • Line Interface
  • Jitter Attenuator
  • Framer/Formatter
  • Test and Diagnostics
  • Control Port
• SPECIFICATIONS COMPLIANCE
• BLOCK DIAGRAMS
• PIN FUNCTION DESCRIPTION
  • Transmit PLL
  • Transmit Side
  • Receive Side
  • Controller Interface
    • • Interrupt/JA Clock Source Select 1
      • Data Bus D[7] or Address/Data Bus AD[7]/Transmit Termination Select
      • Data Bus D[6] or Address/Data Bus AD[6]/Transmit Termination Select
      • Data Bus D[3] or Address/Data Bus AD[3]/TS Mode Select
      • Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select 3/Master Out-Slave In
      • Data Bus D[0] or Address/Data Bus AD[0]/Transmit Clock Source Select 0/Master In-Slave Out
      • Address Bus Bit A[6]/MCLK Prescale Select
      • Address Bus Bit A[3]/Line Build-Out Select 1
      • Address Bus Bit A[2]/Line Build-Out Select 0
      • Address Bus Bit A[1]/Transmit AIS
      • Address Bus Bit A[0]/E1 Termination Select
      • Bus Type Select/Transmit and Receive B8ZS/HDB3 Enable
      • Read Input-Data Strobe/Receive Mode Select Bit 2
      • Chip Select/Remote Loopback Enable
      • Write Input (Read/Write)/Transmit Mode Select 3
  • JTAG
  • Line Interface
  • Power
• PINOUT
• HARDWARE CONTROLLER INTERFACE
  • Transmit Clock Source
  • Internal Termination
  • Line Build-Out
  • Receiver Operating Modes
  • Transmitter Operating Modes
  • MCLK Pre-Scaler
  • Other Hardware Controller Mode Features
• PROCESSOR INTERFACE
  • Parallel Port Functional Description
  • SPI Serial Port Interface Functional Description
    • Clock Phase and Polarity
    • Bit Order
    • Control Byte
    • Burst Mode
    • Register Writes
    • Register Reads
  • Register Map
    • Power-Up Sequence
    • Test Reset Register
    • Mode Configuration Register
  • Interrupt Handling
  • Status Registers
  • Information Registers
  • Interrupt Information Registers
• T1 FRAMER/FORMATTER CONTROL REGISTERS
  • T1 Control Registers
• E1 FRAMER/FORMATTER CONTROL REGISTERS
  • E1 Control Registers
  • E1 Information Registers
• I/O PIN CONFIGURATION OPTIONS
• T1 SYNCHRONIZATION STATUS MESSAGE
  • T1 Bit-Oriented Code (BOC) Controller
  • Transmit BOC
  • Receive BOC
• E1 SYNCHRONIZATION STATUS MESSAGE
  • Sa/Si Bit Access Based on CRC4 Multiframe
  • Alternate Sa/Si Bit Access Based on Double-Frame
• LINE INTERFACE UNIT (LIU)
  • LIU Operation
  • LIU Receiver
    • Receive Level Indicator
    • Receive G.703 Section 10 Synchronization Signal
    • Monitor Mode
  • LIU Transmitter
    • Transmit Short-Circuit Detector/Limiter
    • Transmit Open-Circuit Detector
    • Transmit BPV Error Insertion
    • Transmit G.703 Section 10 Synchronization Signal (E1 Mode)
  • MCLK Pre-Scaler
  • Jitter Attenuator
  • CMI (Code Mark Inversion) Option
  • LIU Control Registers
  • Recommended Circuits
  • Component Specifications
• LOOPBACK CONFIGURATION
• 6312kHz SYNCHRONIZATION INTERFACE
  • Receive 6312kHz Synchronization Interface Operation
  • Transmit 6312kHz Synchronization Interface Operation
• JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
  • Instruction Register
  • Test Registers
  • Boundary Scan Register
  • Bypass Register
  • Identification Register
• FUNCTIONAL TIMING DIAGRAMS
  • Processor Interface
    • Parallel Port Mode
    • SPI Serial Port Mode
• OPERATING PARAMETERS
• AC TIMING PARAMETERS AND DIAGRAMS
  • Multiplexed Bus
  • Nonmultiplexed Bus
  • Serial Bus
  • Receive Side AC Characteristics
  • Transmit Side AC Characteristics
• REVISION HISTORY
• PACKAGE INFORMATION