Rainbow Electronics DS26503 User Manual
General description, Applications, Ordering information
1 of 123
REV: 070904
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GENERAL DESCRIPTION
The DS26503 is a building-integrated timing-
supply (BITS) clock-recovery element. The
receiver portion can recover a clock from T1,
E1, and 6312kHz synchronization timing
interfaces. In T1 and E1 modes, the
Synchronization Status Message (SSM) can also
be recovered. The transmit portion can directly
interface to T1 or E1 interfaces as well as source
the SSM in T1 and E1 modes. The DS26503 can
translate between any of the supported inbound
synchronization clock rates to any supported
outbound rate. A separate output is provided to
source a 6312kHz clock. The device is
controlled through a parallel, serial, or hardware
controller port.
APPLICATIONS
BITS Timing
Rate Conversion
Basic Transceiver
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS26503L
0°C to +70°C
64 LQFP
DS26503LN -40°C to +85°C 64 LQFP
FEATURES
§
G.703 2048kHz Synchronization Interface
Compliant
§
G.703 6312kHz Japanese Synchronization
Interface Compliant
§
Interfaces to Standard T1/J1 (1.544MHz) and
E1 (2.048MHz)
§
Interface to CMI-Coded T1/J1 and E1
§
Short- and Long-Haul Line Interface
§
Transmit and Receive T1 and E1 SSM
Messages with Message Validation
§
Crystal-Less Jitter Attenuator with Bypass
Mode
§
Fully Independent Transmit and Receive
Functionality
§
Internal Software-Selectable Receive- and
Transmit-Side Termination for
75Ω/100Ω/110Ω/120Ω
§
Monitor Mode for Bridging Applications
§
Accepts 16.384MHz, 8.192MHz, 4.096MHz,
2.048MHz, or 1.544MHz (T1 Only) Master
Clock
§
8-Bit Parallel Control Port, Multiplexed or
Nonmultiplexed, Intel or Motorola
§
Serial (SPI) Control Port
§
Hardware Control Mode
§
Provides LOS, AIS, and LOF Indications
Through Hardware Output Pins
§
Fast Transmitter-Output Disable Through
Device Pin for Protection Switching
§
IEEE 1149.1 JTAG Boundary Scan
§
3.3V Supply with 5V-Tolerant Inputs and
Outputs
DS26503
T1/E1/J1 BITS Element
www.maxim-ic.com
Document Outline
- FEATURES
- SPECIFICATIONS COMPLIANCE
- BLOCK DIAGRAMS
- PIN FUNCTION DESCRIPTION
- Transmit PLL
- Transmit Side
- Receive Side
- Controller Interface
-
- Interrupt/JA Clock Source Select 1
- Data Bus D[7] or Address/Data Bus AD[7]/Transmit Termination Select
- Data Bus D[6] or Address/Data Bus AD[6]/Transmit Termination Select
- Data Bus D[3] or Address/Data Bus AD[3]/TS Mode Select
- Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select 3/Master Out-Slave In
- Data Bus D[0] or Address/Data Bus AD[0]/Transmit Clock Source Select 0/Master In-Slave Out
- Address Bus Bit A[6]/MCLK Prescale Select
- Address Bus Bit A[3]/Line Build-Out Select 1
- Address Bus Bit A[2]/Line Build-Out Select 0
- Address Bus Bit A[1]/Transmit AIS
- Address Bus Bit A[0]/E1 Termination Select
- Bus Type Select/Transmit and Receive B8ZS/HDB3 Enable
- Read Input-Data Strobe/Receive Mode Select Bit 2
- Chip Select/Remote Loopback Enable
- Write Input (Read/Write)/Transmit Mode Select 3
-
- JTAG
- Line Interface
- Power
- PINOUT
- HARDWARE CONTROLLER INTERFACE
- PROCESSOR INTERFACE
- T1 FRAMER/FORMATTER CONTROL REGISTERS
- E1 FRAMER/FORMATTER CONTROL REGISTERS
- I/O PIN CONFIGURATION OPTIONS
- T1 SYNCHRONIZATION STATUS MESSAGE
- E1 SYNCHRONIZATION STATUS MESSAGE
- LINE INTERFACE UNIT (LIU)
- LOOPBACK CONFIGURATION
- 6312kHz SYNCHRONIZATION INTERFACE
- JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
- FUNCTIONAL TIMING DIAGRAMS
- OPERATING PARAMETERS
- AC TIMING PARAMETERS AND DIAGRAMS
- REVISION HISTORY
- PACKAGE INFORMATION