Document Outline

• Cover
• Keep safety first in your circuit designs!
• Notes regarding these materials
• General Precautions on Handling of Product
• Configuration of This Manual
• Preface
• Contents
• Figures
• Tables
• Section 1 Overview
  • 1.1 Features
  • 1.2 Internal Block Diagram
  • 1.3 Pin Description
    • 1.3.1 Pin Arrangement
    • 1.3.2 Pin Functions in Each Operating Mode
    • 1.3.3 Pin Functions
• Section 2 CPU
  • 2.1 Features
    • 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
    • 2.1.2 Differences from H8/300 CPU
    • 2.1.3 Differences from H8/300H CPU
  • 2.2 CPU Operating Modes
    • 2.2.1 Normal Mode
    • 2.2.2 Advanced Mode
  • 2.3 Address Space
  • 2.4 Register Configuration
    • 2.4.1 General Registers
    • 2.4.2 Program Counter (PC)
    • 2.4.3 Extended Control Register (EXR)
    • 2.4.4 Condition-Code Register (CCR)
    • 2.4.5 Initial Register Values
  • 2.5 Data Formats
    • 2.5.1 General Register Data Formats
    • 2.5.2 Memory Data Formats
  • 2.6 Instruction Set
    • 2.6.1 Table of Instructions Classified by Function
    • 2.6.2 Basic Instruction Formats
  • 2.7 Addressing Modes and Effective Address Calculation
    • 2.7.1 Register Direct—Rn
    • 2.7.2 Register Indirect—@ERn
    • 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
    • 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
    • 2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
    • 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32
    • 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
    • 2.7.8 Memory Indirect—@@aa:8
    • 2.7.9 Effective Address Calculation
  • 2.8 Processing States
  • 2.9 Usage Notes
    • 2.9.1 Note on TAS Instruction Usage
    • 2.9.2 Note on STM/LDM Instruction Usage
    • 2.9.3 Note on Bit Manipulation Instructions
    • 2.9.4 EEPMOV Instruction
• Section 3 MCU Operating Modes
  • 3.1 MCU Operating Mode Selection
  • 3.2 Register Descriptions
    • 3.2.1 Mode Control Register (MDCR)
    • 3.2.2 System Control Register (SYSCR)
    • 3.2.3 Serial Timer Control Register (STCR)
  • 3.3 Operating Mode Descriptions
    • 3.3.1 Mode 2
    • 3.3.2 Mode 3
  • 3.4 Address Map
• Section 4 Exception Handling
  • 4.1 Exception Handling Types and Priority
  • 4.2 Exception Sources and Exception Vector Table
  • 4.3 Reset
    • 4.3.1 Reset Exception Handling
    • 4.3.2 Interrupts after Reset
    • 4.3.3 On-Chip Peripheral Modules after Reset is Cancelled
  • 4.4 Interrupt Exception Handling
  • 4.5 Trap Instruction Exception Handling
  • 4.6 Stack Status after Exception Handling
  • 4.7 Usage Note
• Section 5 Interrupt Controller
  • 5.1 Features
  • 5.2 Input/Output Pins
  • 5.3 Register Descriptions
    • 5.3.1 Interrupt Control Registers A to C (ICRA to ICRC)
    • 5.3.2 Address Break Control Register (ABRKCR)
    • 5.3.3 Break Address Registers A to C (BARA to BARC)
    • 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)
    • 5.3.5 IRQ Enable Register (IER)
    • 5.3.6 IRQ Status Register (ISR)
    • 5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Register (WUEMRB)
  • 5.4 Interrupt Sources
    • 5.4.1 External Interrupts
    • 5.4.2 Internal Interrupts
  • 5.5 Interrupt Exception Handling Vector Table
  • 5.6 Interrupt Control Modes and Interrupt Operation
    • 5.6.1 Interrupt Control Mode 0
    • 5.6.2 Interrupt Control Mode 1
    • 5.6.3 Interrupt Exception Handling Sequence
    • 5.6.4 Interrupt Response Times
  • 5.7 Address Break
    • 5.7.1 Features
    • 5.7.2 Block Diagram
    • 5.7.3 Operation
    • 5.7.4 Usage Notes
  • 5.8 Usage Notes
    • 5.8.1 Conflict between Interrupt Generation and Disabling
    • 5.8.2 Instructions that Disable Interrupts
    • 5.8.3 Interrupts during Execution of EEPMOV Instruction
    • 5.8.4 IRQ Status Register (ISR)
• Section 6 Bus Controller (BSC)
  • 6.1 Register Descriptions
    • 6.1.1 Bus Control Register (BCR)
    • 6.1.2 Wait State Control Register (WSCR)
• Section 7 I/O Ports
  • 7.1 Port 1
    • 7.1.1 Port 1 Data Direction Register (P1DDR)
    • 7.1.2 Port 1 Data Register (P1DR)
    • 7.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)
    • 7.1.4 Pin Functions
    • 7.1.5 Port 1 Input Pull-Up MOS
  • 7.2 Port 2
    • 7.2.1 Port 2 Data Direction Register (P2DDR)
    • 7.2.2 Port 2 Data Register (P2DR))
    • 7.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)
    • 7.2.4 Pin Functions
    • 7.2.5 Port 2 Input Pull-Up MOS
  • 7.3 Port 3
    • 7.3.1 Port 3 Data Direction Register (P3DDR)
    • 7.3.2 Port 3 Data Register (P3DR)
    • 7.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)
    • 7.3.4 Pin Functions
    • 7.3.5 Port 3 Input Pull-Up MOS
  • 7.4 Port 4
    • 7.4.1 Port 4 Data Direction Register (P4DDR)
    • 7.4.2 Port 4 Data Register (P4DR)
    • 7.4.3 Pin Functions
  • 7.5 Port 5
    • 7.5.1 Port 5 Data Direction Register (P5DDR)
    • 7.5.2 Port 5 Data Register (P5DR)
    • 7.5.3 Pin Functions
  • 7.6 Port 6
    • 7.6.1 Port 6 Data Direction Register (P6DDR)
    • 7.6.2 Port 6 Data Register (P6DR)
    • 7.6.3 Port 6 Pull-Up MOS Control Register (KMPCR)
    • 7.6.4 System Control Register 2 (SYSCR2)
    • 7.6.5 Pin Functions
    • 7.6.6 Port 6 Input Pull-Up MOS
  • 7.7 Port 7
    • 7.7.1 Port 7 Input Data Register (P7PIN)
    • 7.7.2 Pin Functions
  • 7.8 Port 8
    • 7.8.1 Port 8 Data Direction Register (P8DDR)
    • 7.8.2 Port 8 Data Register (P8DR)
    • 7.8.3 Pin Functions
  • 7.9 Port 9
    • 7.9.1 Port 9 Data Direction Register (P9DDR)
    • 7.9.2 Port 9 Data Register (P9DR)
    • 7.9.3 Pin Functions
  • 7.10 Port A
    • 7.10.1 Port A Data Direction Register (PADDR)
    • 7.10.2 Port A Output Data Register (PAODR)
    • 7.10.3 Port A Input Data Register (PAPIN)
    • 7.10.4 Pin Functions
    • 7.10.5 Port A Input Pull-Up MOS
  • 7.11 Port B
    • 7.11.1 Port B Data Direction Register (PBDDR)
    • 7.11.2 Port B Output Data Register (PBODR)
    • 7.11.3 Port B Input Data Register (PBPIN)
    • 7.11.4 Pin Functions
    • 7.11.5 Port B Input Pull-Up MOS
  • 7.12 Ports C, D
    • 7.12.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR)
    • 7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR)
    • 7.12.3 Port C and Port D Input Data Registers (PCPIN, PDPIN)
    • 7.12.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR)
    • 7.12.5 Pin Functions
    • 7.12.6 Input Pull-Up MOS in Ports C and D
  • 7.13 Ports E, F
    • 7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR)
    • 7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR)
    • 7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)
    • 7.13.4 Pin Functions
    • 7.13.5 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)
    • 7.13.6 Pin Functions
    • 7.13.7 Input Pull-Up MOS in Ports E and F
  • 7.14 Port G
    • 7.14.1 Port G Data Direction Register (PGDDR)
    • 7.14.2 Port G Output Data Register (PGODR)
    • 7.14.3 Port G Input Data Register (PGPIN)
    • 7.14.4 Pin Functions
    • 7.14.5 Port G Nch-OD Control Register (PGNOCR)
    • 7.14.6 Pin Functions
• Section 8 8-Bit PWM Timer (PWM)
  • 8.1 Features
  • 8.2 Input/Output Pins
  • 8.3 Register Descriptions
    • 8.3.1 PWM Register Select (PWSL)
    • 8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0)
    • 8.3.3 PWM Data Polarity Register A (PWDPRA)
    • 8.3.4 PWM Output Enable Register A (PWOERA)
    • 8.3.5 Peripheral Clock Select Register (PCSR)
  • 8.4 Operation
    • 8.4.1 PWM Setting Example
    • 8.4.2 Diagram of PWM Used as D/A Converter
  • 8.5 Usage Notes
    • 8.5.1 Module Stop Mode Setting
• Section 9 16-Bit Free-Running Timer (FRT)
  • 9.1 Features
  • 9.2 Input/Output Pins
  • 9.3 Register Descriptions
    • 9.3.1 Free-Running Counter (FRC)
    • 9.3.2 Output Compare Registers A and B (OCRA, OCRB)
    • 9.3.3 Input Capture Registers A to D (ICRA to ICRD)
    • 9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF)
    • 9.3.5 Output Compare Register DM (OCRDM)
    • 9.3.6 Timer Interrupt Enable Register (TIER)
    • 9.3.7 Timer Control/Status Register (TCSR)
    • 9.3.8 Timer Control Register (TCR)
    • 9.3.9 Timer Output Compare Control Register (TOCR)
  • 9.4 Operation
    • 9.4.1 Pulse Output
  • 9.5 Operation Timing
    • 9.5.1 FRC Increment Timing
    • 9.5.2 Output Compare Output Timing
    • 9.5.3 FRC Clear Timing
    • 9.5.4 Input Capture Input Timing
    • 9.5.5 Buffered Input Capture Input Timing
    • 9.5.6 Timing of Input Capture Flag (ICF) Setting
    • 9.5.7 Timing of Output Compare Flag (OCF) setting
    • 9.5.8 Timing of FRC Overflow Flag Setting
    • 9.5.9 Automatic Addition Timing
    • 9.5.10 Mask Signal Generation Timing
  • 9.6 Interrupt Sources
  • 9.7 Usage Notes
    • 9.7.1 Conflict between FRC Write and Clear
    • 9.7.2 Conflict between FRC Write and Increment
    • 9.7.3 Conflict between OCR Write and Compare-Match
    • 9.7.4 Switching of Internal Clock and FRC Operation
    • 9.7.5 Module Stop Mode Setting
• Section 10 8-Bit Timer (TMR)
  • 10.1 Features
  • 10.2 Input/Output Pins
  • 10.3 Register Descriptions
    • 10.3.1 Timer Counter (TCNT)
    • 10.3.2 Time Constant Register A (TCORA)
    • 10.3.3 Time Constant Register B (TCORB)
    • 10.3.4 Timer Control Register (TCR)
    • 10.3.5 Timer Control/Status Register (TCSR)
    • 10.3.6 Time Constant Register (TCORC)
    • 10.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A)
    • 10.3.8 Timer Input Select Register (TISR and TISR_B)
    • 10.3.9 Timer Connection Register I (TCONRI)
    • 10.3.10 Timer Connection Register S (TCONRS)
    • 10.3.11 Timer XY Control Register (TCRXY)
    • 10.3.12 Timer AB Control Register (TCRAB)
  • 10.4 Operation
    • 10.4.1 Pulse Output
  • 10.5 Operation Timing
    • 10.5.1 TCNT Count Timing
    • 10.5.2 Timing of CMFA and CMFB Setting at Compare-Match
    • 10.5.3 Timing of Timer Output at Compare-Match
    • 10.5.4 Timing of Counter Clear at Compare-Match
    • 10.5.5 TCNT External Reset Timing
    • 10.5.6 Timing of Overflow Flag (OVF) Setting
  • 10.6 TMR_0 and TMR_1 Cascaded Connection
    • 10.6.1 16-Bit Count Mode
    • 10.6.2 Compare-Match Count Mode
  • 10.7 TMR_Y and TMR_X Cascaded Connection
    • 10.7.1 16-Bit Count Mode
    • 10.7.2 Compare-Match Count Mode
    • 10.7.3 Input Capture Operation
  • 10.8 TMR_B and TMR_A Cascaded Connection
    • 10.8.1 16-Bit Count Mode
    • 10.8.2 Compare-Match Count Mode
    • 10.8.3 Input Capture Operation
  • 10.9 Interrupt Sources
  • 10.10 Usage Notes
    • 10.10.1 Conflict between TCNT Write and Counter Clear
    • 10.10.2 Conflict between TCNT Write and Count-Up
    • 10.10.3 Conflict between TCOR Write and Compare-Match
    • 10.10.4 Conflict between Compare-Matches A and B
    • 10.10.5 Switching of Internal Clocks and TCNT Operation
    • 10.10.6 Mode Setting with Cascaded Connection
    • 10.10.7 Module Stop Mode Setting
• Section 11 Watchdog Timer (WDT)
  • 11.1 Features
  • 11.2 Input/Output Pins
  • 11.3 Register Descriptions
    • 11.3.1 Timer Counter (TCNT)
    • 11.3.2 Timer Control/Status Register (TCSR)
  • 11.4 Operation
    • 11.4.1 Watchdog Timer Mode
    • 11.4.2 Interval Timer Mode
    • 11.4.3 RESO Signal Output Timing
  • 11.5 Interrupt Sources
  • 11.6 Usage Notes
    • 11.6.1 Notes on Register Access
    • 11.6.2 Conflict between Timer Counter (TCNT) Write and Increment
    • 11.6.3 Changing Values of CKS2 to CKS0 Bits
    • 11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode
    • 11.6.5 System Reset by RESO Signal
    • 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes
• Section 12 Serial Communication Interface (SCI)
  • 12.1 Features
  • 12.2 Input/Output Pins
  • 12.3 Register Descriptions
    • 12.3.1 Receive Shift Register (RSR)
    • 12.3.2 Receive Data Register (RDR)
    • 12.3.3 Transmit Data Register (TDR)
    • 12.3.4 Transmit Shift Register (TSR)
    • 12.3.5 Serial Mode Register (SMR)
    • 12.3.6 Serial Control Register (SCR)
    • 12.3.7 Serial Status Register (SSR)
    • 12.3.8 Serial Interface Mode Register (SCMR)
    • 12.3.9 Bit Rate Register (BRR)
    • 12.3.10 Serial Pin Select Register (SPSR)
  • 12.4 Operation in Asynchronous Mode
    • 12.4.1 Data Transfer Format
    • 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
    • 12.4.3 Clock
    • 12.4.4 SCI Initialization (Asynchronous Mode)
    • 12.4.5 Data Transmission (Asynchronous Mode)
    • 12.4.6 Serial Data Reception (Asynchronous Mode)
  • 12.5 Multiprocessor Communication Function
    • 12.5.1 Multiprocessor Serial Data Transmission
    • 12.5.2 Multiprocessor Serial Data Reception
  • 12.6 Operation in Clocked Synchronous Mode
    • 12.6.1 Clock
    • 12.6.2 SCI Initialization (Clocked Synchronous Mode)
    • 12.6.3 Serial Data Transmission (Clocked Synchronous Mode)
    • 12.6.4 Serial Data Reception (Clocked Synchronous Mode)
    • 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
  • 12.7 Interrupt Sources
  • 12.8 Usage Notes
    • 12.8.1 Module Stop Mode Setting
    • 12.8.2 Break Detection and Processing
    • 12.8.3 Mark State and Break Detection
    • 12.8.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
    • 12.8.5 Relation between Writing to TDR and TDRE Flag
    • 12.8.6 SCI Operations during Mode Transitions
    • 12.8.7 Switching from SCK Pins to Port Pins
• Section 13 I2C Bus Interface (IIC)
  • 13.1 Features
  • 13.2 Input/Output Pins
  • 13.3 Register Descriptions
    • 13.3.1 I2C Bus Data Register (ICDR)
    • 13.3.2 Slave Address Register (SAR)
    • 13.3.3 Second Slave Address Register (SARX)
    • 13.3.4 I2C Bus Mode Register (ICMR)
    • 13.3.5 I2C Bus Control Register (ICCR)
    • 13.3.6 I2C Bus Status Register (ICSR)
    • 13.3.7 DDC Switch Register (DDCSWR)
    • 13.3.8 I2C Bus Extended Control Register (ICXR)
    • 13.3.9 Port G Control Register (PGCTL)
  • 13.4 Operation
    • 13.4.1 I2C Bus Data Format
    • 13.4.2 Initialization
    • 13.4.3 Master Transmit Operation
    • 13.4.4 Master Receive Operation
    • 13.4.5 Slave Receive Operation
    • 13.4.6 Slave Transmit Operation
    • 13.4.7 IRIC Setting Timing and SCL Control
    • 13.4.8 Noise Canceller
    • 13.4.9 Initialization of Internal State
  • 13.5 Interrupt Sources
  • 13.6 Usage Notes
    • 13.6.1 Module Stop Mode Setting
• Section 14 Keyboard Buffer Controller
  • 14.1 Features
  • 14.2 Input/Output Pins
  • 14.3 Register Descriptions
    • 14.3.1 Keyboard Control Register H (KBCRH)
    • 14.3.2 Keyboard Control Register L (KBCRL)
    • 14.3.3 Keyboard Data Buffer Register (KBBR)
  • 14.4 Operation
    • 14.4.1 Receive Operation
    • 14.4.2 Transmit Operation
    • 14.4.3 Receive Abort
    • 14.4.4 KCLKI and KDI Read Timing
    • 14.4.5 KCLKO and KDO Write Timing
    • 14.4.6 KBF Setting Timing and KCLK Control
    • 14.4.7 Receive Timing
    • 14.4.8 KCLK Fall Interrupt Operation
  • 14.5 Usage Notes
    • 14.5.1 KBIOE Setting and KCLK Falling Edge Detection
    • 14.5.2 Module Stop Mode Setting
• Section 15 Host Interface (LPC)
  • 15.1 Features
  • 15.2 Input/Output Pins
  • 15.3 Register Descriptions
    • 15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)
    • 15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)
    • 15.3.3 LPC Channel 3 Address Register (LADR3)
    • 15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3)
    • 15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)
    • 15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
    • 15.3.7 Status Registers 1 to 3 (STR1 to STR3)
    • 15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)
    • 15.3.9 Host Interface Select Register (HISEL)
  • 15.4 Operation
    • 15.4.1 Host Interface Activation
    • 15.4.2 LPC I/O Cycles
    • 15.4.3 A20 Gate
    • 15.4.4 Host Interface Shutdown Function (LPCPD)
    • 15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ)
    • 15.4.6 Host Interface Clock Start Request (CLKRUN)
  • 15.5 Interrupt Sources
    • 15.5.1 IBFI1, IBFI2, IBFI3, and ERRI
    • 15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12
  • 15.6 Usage Notes
    • 15.6.1 Module Stop Mode Setting
    • 15.6.2 Notes on Using Host Interface
• Section 16 A/D Converter
  • 16.1 Features
  • 16.2 Input/Output Pins
  • 16.3 Register Descriptions
    • 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
    • 16.3.2 A/D Control/Status Register (ADCSR)
    • 16.3.3 A/D Control Register (ADCR)
  • 16.4 Operation
    • 16.4.1 Single Mode
    • 16.4.2 Scan Mode
    • 16.4.3 Input Sampling and A/D Conversion Time
    • 16.4.4 External Trigger Input Timing
  • 16.5 Interrupt Sources
  • 16.6 A/D Conversion Accuracy Definitions
  • 16.7 Usage Notes
    • 16.7.1 Permissible Signal Source Impedance
    • 16.7.2 Influences on Absolute Accuracy
    • 16.7.3 Setting Range of Analog Power Supply and Other Pins
    • 16.7.4 Notes on Board Design
    • 16.7.5 Notes on Noise Countermeasures
    • 16.7.6 Module Stop Mode Setting
• Section 17 RAM
• Section 18 ROM
  • 18.1 Features
  • 18.2 Mode Transitions
  • 18.3 Block Configuration
  • 18.4 Input/Output Pins
  • 18.5 Register Descriptions
    • 18.5.1 Flash Memory Control Register 1 (FLMCR1)
    • 18.5.2 Flash Memory Control Register 2 (FLMCR2)
    • 18.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
  • 18.6 Operating Modes
  • 18.7 On-Board Programming Modes
    • 18.7.1 Boot Mode
    • 18.7.2 User Program Mode
  • 18.8 Flash Memory Programming/Erasing
    • 18.8.1 Program/Program-Verify
    • 18.8.2 Erase/Erase-Verify
  • 18.9 Program/Erase Protection
    • 18.9.1 Hardware Protection
    • 18.9.2 Software Protection
    • 18.9.3 Error Protection
  • 18.10 Interrupts during Flash Memory Programming/Erasing
  • 18.11 Programmer Mode
  • 18.12 Usage Notes
• Section 19 Clock Pulse Generator
  • 19.1 Oscillator
    • 19.1.1 Connecting Crystal Resonator
    • 19.1.2 External Clock Input Method
  • 19.2 Duty Correction Circuit
  • 19.3 Medium-Speed Clock Divider
  • 19.4 Bus Master Clock Select Circuit
  • 19.5 Subclock Input Circuit
  • 19.6 Waveform Forming Circuit
  • 19.7 Clock Select Circuit
  • 19.8 Usage Notes
    • 19.8.1 Note on Resonator
    • 19.8.2 Notes on Board Design
• Section 20 Power-Down Modes
  • 20.1 Register Descriptions
    • 20.1.1 Standby Control Register (SBYCR)
    • 20.1.2 Low-Power Control Register (LPWRCR)
    • 20.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
  • 20.2 Mode Transitions and LSI States
  • 20.3 Medium-Speed Mode
  • 20.4 Sleep Mode
  • 20.5 Software Standby Mode
  • 20.6 Hardware Standby Mode
  • 20.7 Watch Mode
  • 20.8 Subsleep Mode
  • 20.9 Subactive Mode
  • 20.10 Module Stop Mode
  • 20.11 Direct Transitions
  • 20.12 Usage Notes
    • 20.12.1 I/O Port Status
    • 20.12.2 Current Consumption when Waiting for Oscillation Stabilization
• Section 21 List of Registers
  • 21.1 Register Addresses (Address Order)
  • 21.2 Register Bits
  • 21.3 Register States in Each Operating Mode
  • 21.4 Register Select Conditions
• Section 22 Electrical Characteristics
  • 22.1 Absolute Maximum Ratings
  • 22.2 DC Characteristics
  • 22.3 AC Characteristics
    • 22.3.1 Clock Timing
    • 22.3.2 Control Signal Timing
    • 22.3.3 Timing of On-Chip Peripheral Modules
  • 22.4 A/D Conversion Characteristics
  • 22.5 Flash Memory Characteristics
  • 22.6 Usage Note
  • 22.7 Timing Chart
    • 22.7.1 Clock Timing
    • 22.7.2 Control Signal Timing
    • 22.7.3 On-Chip Peripheral Module Timing
• Appendix
  • A. I/O Port States in Each Processing State
  • B. Product Codes
  • C. Package Dimensions
• Index
• Colphon
• Address List
• Back Cover